Search results for "bridging faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker	Modeling Feedback Bridging Faults with Non-Zero Resistance.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	feedback bridging faults, resistive bridging faults, bridging fault simulation
4	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
4	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai	Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
3	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Automatic Test Pattern Generation for Resistive Bridging Faults.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	resistive short defects, ATPG, SAT, bridging faults
3	Yukiya Miura, Shuichi Seno	Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis
3	Claude Thibeault	On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Delta ${rm I}_{DDQ}$, probabilistic signatures, diagnosis, Integrated circuits, bridging faults, multiple faults
3	Michele Favalli, Cecilia Metra	Bridging Faults in Pipelined Circuits.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	fault modeling, bridging faults, CMOS circuits, pipelined circuits
3	Chul Young Lee, D. M. H. Walker	PROBE: A PPSFP Simulator for Resistive Bridging Faults.	VTS	2000	DBLP DOI BibTeX RDF	PPSFP, fault model, fault simulation, bridging fault, resistive bridging faults
3	Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana	Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I/sub DDQ/ Testing in BiCMOS and CMOS Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults
3	Alvernon Walker, Algernon P. Henry, Parag K. Lala	An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current
3	Srikanth Venkataraman, W. Kent Fuchs	A deductive technique for diagnosis of bridging faults.	ICCAD	1997	DBLP DOI BibTeX RDF	Diagnosis, Bridging faults, Deduction
3	Sreejit Chakravarty, Paul J. Thadikaran	Algorithms to select IDDQ measurement points to detect bridging faults.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	bridging faults, test selection, I DDQ test
3	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
3	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
3	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
3	Sreejit Chakravarty, Yiming Gong	Voting model based diagnosis of bridging faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure
3	Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee	Diagnosis of realistic bridging faults with single stuck-at information.	ICCAD	1995	DBLP DOI BibTeX RDF	match requirement, match restriction, realistic bridging faults diagnosis, single stuck-at dictionaries, single stuck-at information, stuck-at diagnosis, stuck-at methods, fault diagnosis, logic testing, fault location, failure analysis, failure recovery
3	Michele Favalli, Piero Olivo, Bruno Riccò	Dynamic effects in the detection of bridging faults in CMOS ICs.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	test invalidation, fault models, fault simulation, Bridging faults
3	Sreejit Chakravarty, Minsheng Liu	Algorithms for IDDQ measurement based diagnosis of bridging faults.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	Bridging faults, diagnosis algorithm, I DDQ testing
2	Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	Detectability of internal bridging faults in scan chains.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Partitioned n-detection test generation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets
2	Irith Pomeranz, Sudhakar M. Reddy	Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Using Dummy Bridging Faults to Define Reduced Sets of Target Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Generation of broadside transition fault test sets that detect four-way bridging faults.	DATE	2006	DBLP DOI BibTeX RDF
2	Jack R. Smith, Tian Xia, Charles E. Stroud	An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	stuck-at faults, bridging faults, delay faults
2	Irith Pomeranz, Sudhakar M. Reddy	Dynamic Test Compaction for Bridging Faults.	ISQED	2005	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu	On the characterization and efficient computation of hard-to-detect bridging faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Baris Arslan, Alex Orailoglu	Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
2	Mehdi Baradaran Tahoori	Application-dependent testing of FPGAs for bridging faults.	FPGA	2003	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu	On the Characterization of Hard-to-Detect Bridging Faults.	DATE	2003	DBLP DOI BibTeX RDF
2	Ilia Polian, Piet Engelke, Bernd Becker	Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	Voting models, Fault simulation, Bridging faults
2	Claude Thibeault	Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm.	VTS	2000	DBLP DOI BibTeX RDF	probabilistic signatures, double faults, Diagnosis, Viterbi algorithm, Delta Iddq
2	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.	IOLTW	2000	DBLP DOI BibTeX RDF	BIST, Random Testing, Delay Testing, Bridging Faults
2	Charles E. Stroud, James R. Bailey, Johan R. Emmert	A New Method for Testing Re-Programmable PLAs.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	electrically erasable programmable logic array testing, manufacturing test development, bridging faults
2	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang	BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF
2	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Identification of Feedback Bridging Faults with Oscillation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	feedback bridging fault, CMOS, logic circuit, oscillation
2	Irith Pomeranz, Sudhakar M. Reddy	Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	test generation, fault simulation, stuck-at faults, bridging faults, circuit partitioning
2	Brian Chess, Tracy Larrabee	Logic Testing of Bridging Faults in CMOS Integrated Circuits.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	realistic faults, fault models, fault simulation, test pattern generation, Bridging faults
2	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
2	David B. Lavo, Brian Chess, Tracy Larrabee, F. Joel Ferguson	Diagnosing realistic bridging faults with single stuck-at information.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Yiming Gong, Sreejit Chakravarty	Locating bridging faults using dynamically computed stuck-at fault dictionaries.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.	ITC	1998	DBLP DOI BibTeX RDF	IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase
2	Vijay R. Sar-Dessai, D. M. H. Walker	Accurate Fault Modeling and Fault Simulation of Resistive Bridges. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	realistic bridges, zero-ohm bridges, Resistive bridging faults, low-voltage testing
2	Claude Thibeault, Luc Boisvert	On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	current signatures, diagnosis, Integrated circuits, bridging faults, Iddq testing
2	Yiming Gong, Sreejit Chakravarty	Using fault sampling to compute I/sub DDQ/ diagnostic test set.	VTS	1997	DBLP DOI BibTeX RDF	fault sampling, IDDQ diagnostic test set generation, combinational circuits, combinational circuit, bridging faults
2	Sreejit Chakravarty, Paul J. Thadikaran	Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	test generation, fault simulation, Bridging faults, IDDQ testing
2	Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya	Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
2	Peter Dahlgren, Peter Lidén	A fault model for switch-level simulation of gate-to-drain shorts.	VTS	1996	DBLP DOI BibTeX RDF	switch-level simulation, gate-to-drain shorts, transistor-level bridging faults, network primitive, electrical-level analysis, algorithm, fault diagnosis, fault model, iteration, integrated circuit modelling, subnetworks
2	Salvador Manich, Michael Nicolaidis, Joan Figueras	Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring.	VTS	1996	DBLP DOI BibTeX RDF	mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness
2	Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs	Circuit-level dictionaries of CMOS bridging faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Miquel Roca, Antonio Rubio	Current testability analysis of feedback bridging faults in CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
2	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
2	Michel Renovell, P. Huc, Yves Bertrand	The concept of resistance interval: a new parametric model for realistic resistive bridging fault.	VTS	1995	DBLP DOI BibTeX RDF	electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior
2	S. Wayne Bollinger, Scott F. Midkiff	Test generation for IDDQ testing of bridging faults in CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò	Fault simulation of parametric bridging faults in CMOS IC's.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
2	Kuen-Jong Lee, Melvin A. Breuer	Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
2	Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana	Limitations of switch level analysis for bridging faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
2	Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana	On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates.	DAC	1987	DBLP DOI BibTeX RDF
2	Miron Abramovici, Premachandran R. Menon	A Practical Approach to Fault Simulation and Test Generation for Bridging Faults.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	test generation, fault detection, fault simulation, Bridging faults
2	Mark G. Karpovsky	Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	upper and lower bounds for number of tests, Asymptotically optimal tests, stuck-at and bridging faults, universal tests, fault detection
2	Teruhiko Yamada, Takashi Nanya	Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines".	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Asynchronous behavior, test generation, fault detection, fault location, bridging faults, combinational networks
1	Avik Chakraborty	Testing of Bridging Faults in AND-EXOR based Reversible Logic Circuits	CoRR	2010	DBLP BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On multiple bridging faults.	VTS	2010	DBLP DOI BibTeX RDF
1	Ho-Yong Choi, Kewal K. Saluja	Detection of inter-port bridging faults in dual-port memories.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration.	VLSI Design	2010	DBLP DOI BibTeX RDF	interconnect open faults, test generation, bridging faults, static test compaction
1	Michele Favalli, Cecilia Metra	Testing Resistive Opens and Bridging Faults Through Pulse Propagation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian	SUPERB: Simulator utilizing parallel evaluation of resistive bridges.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PPSFP, SPPFP, fault mapping, Resistive bridging faults, bridging fault simulation
1	Michele Favalli, Marcello Dalpasso	How Many Test Vectors We Need to Detect a Bridging Fault?	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	Test generation, Fault simulation, Bridging faults
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute	Comprehensive bridging fault diagnosis based on the SLAT paradigm.	DDECS	2009	DBLP DOI BibTeX RDF
1	Juraj Brenkus, Viera Stopjaková, Ronny Vanhooren, Anton Chichkov	Comparison of different test strategies on a mixed-signal circuit.	DDECS	2009	DBLP DOI BibTeX RDF
1	Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin, James Chien-Mo Li	Diagnosis of Logic-to-chain Bridging Faults.	ITC	2008	DBLP DOI BibTeX RDF
1	S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod	Bridge Defect Diagnosis for Multiple-Voltage Design.	European Test Symposium	2008	DBLP DOI BibTeX RDF	Logic based Diagnosis, Multiple-Vdd designs, Resistive Bridging Faults
1	Irith Pomeranz, Sudhakar M. Reddy	Safe Fault Collapsing Based on Dominance Relations.	European Test Symposium	2008	DBLP DOI BibTeX RDF	test generation, bridging faults, fault collapsing, dominance relations
1	Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang	A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	profiling, design for testability, Diagnosis, fault, scan chain
1	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
1	Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC.	DSD	2008	DBLP DOI BibTeX RDF
1	Michele Favalli, Marcello Dalpasso	High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations.	DFT	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Forming N-detection test sets without test generation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	test generation, stuck-at faults, Bridging faults, n-detection test sets
1	Michele Favalli, Cecilia Metra	Interactive presentation: Pulse propagation for the detection of small delay defects.	DATE	2007	DBLP DOI BibTeX RDF
1	Shahin Golshan, Elaheh Bozorgzadeh	Single-Event-Upset (SEU) Awareness in FPGA Routing.	DAC	2007	DBLP DOI BibTeX RDF
1	Hugo Cheung, Sandeep K. Gupta	Accurate modeling and fault simulation of Byzantine resistive bridges.	ICCD	2007	DBLP DOI BibTeX RDF
1	Pallav Gupta, Niraj K. Jha, Loganathan Lingappan	A Test Generation Framework for Quantum Cellular Automata Circuits.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Pallav Gupta, Niraj K. Jha, Loganathan Lingappan	Test generation for combinational quantum cellular automata (QCA) circuits.	DATE	2006	DBLP DOI BibTeX RDF
1	Xinyue Fan, Will R. Moore, Camelia Hora, Mario H. Konijnenburg, Guido Gronthoud	A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis.	VTS	2006	DBLP DOI BibTeX RDF
1	Xijiang Lin, Janusz Rajski	The Impacts of Untestable Defects on Transition Fault Testing.	VTS	2006	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori	Application-Dependent Testing of FPGAs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker	Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.	VTS	2005	DBLP DOI BibTeX RDF	Deep submicron technology modeling, Resistive bridging faults
1	Hafizur Rahaman, Debesh K. Das	Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar	On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Zhigang Jiang, Sandeep K. Gupta	Threshold testing: Covering bridging and other realistic faults.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy	On Improving Defect Coverage of Stuck-at Fault Tests.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni	A Built-In Self-Test Scheme for Differential Ring Oscillators.	ISQED	2005	DBLP DOI BibTeX RDF
1	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan	Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF	Complex Logic Blocks, Routing Errors, Vertex Coloring problem, Fault Tolerance, Field Programmable Gate Arrays, Graph Theory, Single Event Upset
1	Jiang Brandon Liu, Andreas G. Veneris	Incremental fault diagnosis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-independent testing of FPGA interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits.	IEICE Transactions	2004	DBLP BibTeX RDF
1	Yukiya Miura	Analysis and Testing of Bridging Faults in CMOS Synchronous Sequential Circuits.	IEICE Transactions	2004	DBLP BibTeX RDF