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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9 occurrences of 5 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hua Wang, Francky Catthoor, Miguel Miranda, Wim Dehaene |
Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs.  |
Signal Processing Systems  |
2008 |
DBLP DOI BibTeX RDF |
CMOS buffer, Low power design, Trade-offs |
| 1 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Low-power fanout optimization using MTCMOS and multi-Vt techniques. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
buffer chain, fanout tree, low-power design, fanout optimization |
| 1 | Fei Yuan, Minghai Li |
A new area-efficient 4-PAM 10 Gb/s CMOS serial link transmitter. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Low-power fanout optimization using multiple threshold voltage inverters. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
buffer chain, fanout tree, low-power design, fanout optimization |
| 1 | Ali Bastani, Charles A. Zukowski |
Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
gate leakage reduction, superbuffers, low power design |
| 1 | Shrutin Ulman |
Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija |
CMOS Combinational Circuit Sizing by Stage-wise Tapering. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
tapering, Transistor sizing, resynthesis |
Displaying result #1 - #7 of 7 (100 per page; Change: )
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