|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 107 occurrences of 77 keywords
|
|
|
|
|
Results
Found 18 publication records. Showing 18 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Zhi-Gang Wu, Hao Luo, Shuzhuang Zhang, Tao Zhang |
TCP Connection Management Model in Complex Topology Network.  |
ICGEC  |
2011 |
DBLP DOI BibTeX RDF |
complex topology, client/server, bus, connection management |
| 1 | Fangyong Hou, Hongjun He, Nong Xiao, Fang Liu, Guangjun Zhong |
Efficient Encryption-Authentication of Shared Bus-Memory in SMP System.  |
CIT  |
2010 |
DBLP DOI BibTeX RDF |
Authentication, Encryption, Shared Memory, Bus |
| 1 | Petr Krist |
Advanced Industrial Communications.  |
Towards Intelligent Engineering and Information Technology  |
2009 |
DBLP DOI BibTeX RDF |
CANopen, Ethernet Powerlink, NMT, solunode, PDO, RS-485, SDO, slave, communication, network, protocol, coding, Ethernet, TDMA, frame, CAN, layer, bus, bit-rate, master, fieldbus, Fast Ethernet |
| 1 | DiaaEldin Khalil, Yehea I. Ismail |
A global interconnect link design for many-core microprocessors.  |
IFMT  |
2008 |
DBLP DOI BibTeX RDF |
interconnect, link, bus, repeater insertion |
| 1 | Arvind Ashok, Christian M. Beck, Nick Quagliara |
Ri-Ri: assisting bus conductors in madras (chennai).  |
CHI Extended Abstracts  |
2007 |
DBLP DOI BibTeX RDF |
CHI 2007, Madras, transportation, bus, MTC |
| 1 | Fan Mo, Robert K. Brayton |
Semi-detailed bus routing with variation reduction.  |
ISPD  |
2007 |
DBLP DOI BibTeX RDF |
routing, variation, bus |
| 1 | Xinping Zhu, Sharad Malik |
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs.  |
ACM Trans. Design Autom. Electr. Syst.  |
2007 |
DBLP DOI BibTeX RDF |
on-chip communication architecture, network-on-chip, multiprocessor system, object-oriented modeling, packet-switching network, design exploration, bus, Retargetable simulation |
| 1 | Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar |
SECA: security-enhanced communication architecture.  |
CASES  |
2005 |
DBLP DOI BibTeX RDF |
AMBA Bus, security-aware design, small embedded systems, security, communication, access control, architecture, intrusion detection, system-on-chip (SoC), attacks, bus, digital rights management (DRM) |
| 1 | Xinping Zhu, Wei Qin, Sharad Malik |
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.  |
CODES+ISSS  |
2004 |
DBLP DOI BibTeX RDF |
on-chip communication architecture, simulator synthesis, multiprocessor system, packet-switching network, design exploration, bus, retargetable simulation |
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.  |
ACM Great Lakes Symposium on VLSI  |
2004 |
DBLP DOI BibTeX RDF |
BFT, scalability, pipelining, bus, MP-SoC |
| 1 | Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III |
Low-power design methodology for an on-chip bus with adaptive bandwidth capability.  |
DAC  |
2003 |
DBLP DOI BibTeX RDF |
low-power, delay, on-chip interconnect, bus, current-mode, point-to-point |
| 1 | Yi Pan, Si-Qing Zheng, Keqin Li, Hong Shen |
An Improved Generalization of Mesh-Connected Computers with Multiple Buses.  |
IEEE Trans. Parallel Distrib. Syst.  |
2001 |
DBLP DOI BibTeX RDF |
mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, Bus, mesh-connected computer |
| 1 | Yi Pan, Si-Qing Zheng, Keqin Li, Hong Shen |
Semigroup and Prefix Computations on Improved Generalized Mesh-Connected Computers with Multiple Buses. (PDF / PS)  |
IPDPS  |
2000 |
DBLP DOI BibTeX RDF |
mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, bus, mesh-connected computer |
| 1 | Peter James Aldworth |
System-on-a-Chip Bus Architecture for Embedded Applications.  |
ICCD  |
1999 |
DBLP DOI BibTeX RDF |
architecture, interconnect, latency, infrastructure, system-on-a-chip, bus, capacitance, peripherals |
| 1 | Pedro A. Molina, Peter Y. K. Cheung |
A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems.  |
ASYNC  |
1997 |
DBLP DOI BibTeX RDF |
Tri-state Buffers, Asynchronous, Composability, Bus, Data Path, Delay-Insensitive, Handshake Circuits |
| 1 | János Sztrik, Demetres D. Kouvatsos |
Asymptotic Analysis of a Heterogeneous Multiprocessor System in a Randomly Changing Environment.  |
IEEE Trans. Software Eng.  |
1991 |
DBLP DOI BibTeX RDF |
asymptotic queuing theoretic approach, heterogeneous multiprocessor computer system, randomly changing environment, stochastic times, random environment, service rates, busy period length, exponentially distributed random variable, steady-state performance measures, mean delay time, expected waiting time, performance evaluation, reliability, queueing theory, multiprocessing systems, stochastic processes, bus, system throughput, FCFS |
| 1 | P. V. Afshari, Steven C. Bruell, Richard Y. Kain |
On the Load Balancing Bus Accessing Scheme.  |
IEEE Trans. Computers  |
1983 |
DBLP DOI BibTeX RDF |
modeling, load balancing, distributed computing, queueing networks, Bus |
| 1 | Werner Bux |
Analysis of a Local-Area Bus System with Controlled Access.  |
IEEE Trans. Computers  |
1983 |
DBLP DOI BibTeX RDF |
scheduling, performance, protocol, Access method, bus, local network |
Displaying result #1 - #18 of 18 (100 per page; Change: )
|
|