Search results for "buses"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Susumu Matsumae, Nobuki Tokura	Simulating a Mesh with Separable Buses by a Mesh with Partitioned Buses.	ISPAN	1999	DBLP DOI BibTeX RDF	two-dimensional mesh-connected computer, mesh with separable buses, mesh with partitioned buses, broadcasting, propagation delay, simulation algorithm
4	Mounir Hamdi, J. Tong, C. W. Kin	Fast sorting algorithms on reconfigurable array of processors with optical buses. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm
4	Jeffrey A. Floyd, Matt Perry	Real-time on-board bus testing.	VTS	1995	DBLP DOI BibTeX RDF	on-board bus testing, wide buses, computer buses, board layout, full-fault testing, multiple speeds, pseudo-random pattern generation, characteristic equations, IEEE JTAG protocol, real-time systems, protocols, logic testing, automatic testing, system buses, operating environments, multiple seed, clock speeds
3	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	Energy-efficient encoding techniques for off-chip data buses.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power data buses, bus switching, internal capacitances, encoding
3	Qingli Zhang, Jinxiang Wang, Yizheng Ye	An energy-efficient temporal encoding circuit technique for on-chip high performance buses.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	on-chip buses, energy-efficient, encoding, repeaters
3	Jun Yang 0002, Rajiv Gupta, Chuanjun Zhang	Frequent value encoding for low power data buses.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
3	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif	Approaches to run-time and standby mode leakage reduction in global buses.	ISLPED	2004	DBLP DOI BibTeX RDF	pulsed buses, leakage, repeaters, MTCMOS
3	Jihong Ren, Mark R. Greenstreet	Synthesizing optimal filters for crosstalk-cancellation for high-speed buses.	DAC	2003	DBLP DOI BibTeX RDF	equalizing filters, optimal synthesis, crosstalk, buses
3	Maged Ghoneima, Yehea I. Ismail	Optimum positioning of interleaved repeaters In bidirectional buses.	DAC	2003	DBLP DOI BibTeX RDF	delay, interconnect, noise, repeaters, buses
3	Yan Zhang, John Lach, Kevin Skadron, Mircea R. Stan	Odd/even bus invert with two-phase transfer for buses with coupling.	ISLPED	2002	DBLP DOI BibTeX RDF	bus invert, buses with coupling, coding for low-power I/O
3	Yi Pan, Si-Qing Zheng, Keqin Li, Hong Shen	An Improved Generalization of Mesh-Connected Computers with Multiple Buses.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, Bus, mesh-connected computer
3	Yi Pan, Si-Qing Zheng, Keqin Li, Hong Shen	Semigroup and Prefix Computations on Improved Generalized Mesh-Connected Computers with Multiple Buses. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, bus, mesh-connected computer
3	Anu G. Bourgeois, Jerry L. Trahan	Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	Reconfigurable models, optical buses, complexity, model simulations
3	Rong Lin, Stephan Olariu, James L. Schwing, Biing-Feng Wang	The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	mesh with hybrid buses, cost-optimal algorithms, pattern recognition, image processing, broadcasting, VLSI architectures, digital geometry, cellular systems
3	Biing-Feng Wang, Stephan Olariu	On the Power of the Mesh with Hybrid Buses.	ISPAN	1997	DBLP DOI BibTeX RDF	Mesh with Hybrid Buses, Mesh with Multiple Broadcasting, simulation, parallel algorithms, PRAM, reconfigurable mesh
3	Kuo-Liang Chung, Yu-Chih Lin	A Parametric Algorithm for Semigroup Computation on Mesh with Buses.	Computing	1996	DBLP DOI BibTeX RDF	mesh-connected computers with segmented buses, reconfigurable buses, parametric parallel algorithm, broadcasting, Semigroup computation
3	Sanguthevar Rajasekaran	Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing and Sorting.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	mesh with reconfigurable buses, mesh with fixed buses, k?k routing, k?k sorting, parallel computing, randomized algorithms, sorting, mesh, packet routing, Reconfigurable networks
3	Sandy Pavel, Selim G. Akl	Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable Optical Buses. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	arrays with reconfigurable optical buses, Hough transform
3	Mounir Hamdi, Yi Pan	Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses.	ISPAN	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
3	Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
3	Mircea R. Stan, Wayne P. Burleson	Coding a terminated bus for low power.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
3	Zicheng Guo, Rami G. Melhem	Embedding Binary X-Trees and Pyramids in Processor Arrays with Spanning Buses.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	binaryX-trees, spanning buses, 2-D arrayarchitectures, routing step, parallel architectures, multiprocessor interconnection networks, embedding, network routing, binary trees, processor arrays, pyramids, network embeddings
3	Mauricio J. Serrano, Behrooz Parhami	Optimal Architectures and Algorithms for Mesh-Connected Parallel Computers with Separable Row/Column Buses.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	mesh-connected, separable row and column buses, parallel algorithms, computational complexity, parallel computers, parallel architectures, time complexity, processing elements, data routing, two-dimensional mesh, prefix computation, semigroup computation
3	Jop F. Sibeyn, Michael Kaufmann, Rajeev Raman	Randomized Routing on Meshes with Buses.	ESA	1993	DBLP DOI BibTeX RDF	algorithms, parallel computation, lower bounds, meshes, coloring, randomization, packet routing, buses
2	Irina Astrova, Arne Koschel, Tobias Kruessmann	Comparison of enterprise service buses based on their support of high availability.	SAC	2010	DBLP DOI BibTeX RDF	fault tolerance, high availability, enterprise service bus
2		Service Buses.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
2	Krishnan Sundaresan, Nihar R. Mahapatra	Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.	ISQED	2008	DBLP DOI BibTeX RDF	Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
2	Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien	Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Qin Li, Huibiao Zhu, Jifeng He	Towards the Service Composition Through Buses.	HASE	2008	DBLP DOI BibTeX RDF
2	Kimish Patel, Wonbok Lee, Massoud Pedram	In-order pulsed charge recycling in off-chip data buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	data buses, power, charge recycling
2	Karthik Duraisami, Enrico Macii, Massimo Poncino	Energy efficiency bounds of pulse-encoded buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	power reduction., pulse wave transmission, high-speed interconnect, transition activity
2	Michel Sede, Xu Li, Da Li, Min-You Wu, Minglu Li, Wei Shu	Routing in Large-Scale Buses Ad Hoc Networks.	WCNC	2008	DBLP DOI BibTeX RDF
2	Dirk Koch, Christian Haubelt, Jürgen Teich	Efficient Reconfigurable On-Chip Buses for FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
2	Tomoya Kitani, Takashi Shinkawa, Naoki Shibata, Keiichi Yasumoto, Minoru Ito, Teruo Higashino	Efficient VANET-Based Traffic Information Sharing using Buses on Regular Routes.	VTC Spring	2008	DBLP DOI BibTeX RDF
2	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Liang Zhang, J. M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon	Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Hanif Fatemi, Behnam Amelifard, Massoud Pedram	Power optimal MTCMOS repeater insertion for global buses.	ISLPED	2007	DBLP DOI BibTeX RDF	MTCMOS circuits, low-power design, buffer insertion
2	Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara	Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.	ASP-DAC	2007	DBLP DOI BibTeX RDF
2	Sharath Jayaprakash, Nihar R. Mahapatra	Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Mohammad Reza Selim, Takumi Endo, Yuichi Goto, Jingde Cheng	Distributed hash table based design of Soft System Buses.	Infoscale	2007	DBLP DOI BibTeX RDF	chord protocol, soft system bus, middleware, distributed hash table
2	Brett H. Meyer, Donald E. Thomas	Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	bus architecture synthesis, embedded multiprocessor systems-on-chip, partitioning, sharing, memory allocation, data mapping
2	Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen	Analytical model for crosstalk and intersymbol interference in point-to-point buses.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	David C. Keezer, Dany Minier, Patrice Ducharme	Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing
2	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Reducing the Data Switching Activity on Serial Link Buses.	ISQED	2006	DBLP DOI BibTeX RDF
2	Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen	Language-Based High Level Transaction Extraction on On-chip Buses.	ISQED	2006	DBLP DOI BibTeX RDF
2	Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie	Delay and Energy Efficient Data Transmission for On-Chip Buses.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam	Delay and peak power minimization for on-chip buses using temporal redundancy.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	low-power, coding, crosstalk
2	Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra	Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	address bus, low power, encoding, energy dissipation
2	Jaroslav Koton, Kamil Vrba, Pavel Hanak	Frequency Filter with Current Conveyors for Signal Processing of Data-Buses Working in the Current-mode.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
2	Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor	Physical design implementation of segmented buses to reduce communication energy.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Qingli Zhang, Jinxiang Wang, Yizheng Ye	Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal	A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Krishnan Sundaresan, Nihar R. Mahapatra	Value-based bit ordering for energy optimization of on-chip global signal buses.	DATE	2006	DBLP DOI BibTeX RDF
2	Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri	Memory-based crosstalk canceling CODECs for on-chip buses.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Armin Fügenschuh	Scheduling Buses and School Starting Times.	OR	2006	DBLP DOI BibTeX RDF
2	Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling	Optimal memoryless encoding for low power off-chip data buses.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Maged Ghoneima, Yehea I. Ismail	Optimum positioning of interleaved repeaters in bidirectional buses.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy	Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	A tunable bus encoder for off-chip data buses.	ISLPED	2005	DBLP DOI BibTeX RDF	TUBE, data bus, data bus encoding, tunable bus encoder
2	Liang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
2	Boon-Chong Seet, Chiew Tong Lau, Wen-Jing Hsu, Bu-Sung Lee	A Mobile System of Super-Peers Using City Buses.	PerCom Workshops	2005	DBLP DOI BibTeX RDF
2	Teck Meng Lim, Boon-Chong Seet, Bu-Sung Lee, Chai Kiat Yeo, Andreas Kassler	Pervasive Communication for Commuters in Public Buses.	PerCom Workshops	2005	DBLP DOI BibTeX RDF
2	Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura	A variation-aware low-power coding methodology for tightly coupled buses.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Jingde Cheng	Connecting Components with Soft System Buses: A New Methodology for Design, Development, and Maintenance of Reconfigurable, Ubiquitous, and Persistent Reactive Systems.	AINA	2005	DBLP DOI BibTeX RDF
2	Krishnan Sundaresan, Nihar R. Mahapatra	An Accurate Energy and Thermal Model for Global Signal Buses.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Maged Ghoneima, Yehea I. Ismail	Accurate decoupling of capacitively coupled buses.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Krishnan Sundaresan, Nihar R. Mahapatra	Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.	HPCA	2005	DBLP DOI BibTeX RDF
2	Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang 0002	VALVE: Variable Length Value Encoder for Off-Chip Data Buses..	ICCD	2005	DBLP DOI BibTeX RDF
2	Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram	Transition reduction in memory buses using sector-based encoding techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Chin-Hsiung Wu, Shi-Jinn Horng	Run-length chain coding and scalable computation of a shape's moments using reconfigurable optical buses.	IEEE Transactions on Systems, Man, and Cybernetics, Part B	2004	DBLP DOI BibTeX RDF
2	Yi Zhao, Sujit Dey, Li Chen	Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Maged Ghoneima, Yehea I. Ismail	Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Mauro Olivieri, Francesco Pappalardo 0002, Giuseppe Visalli	Bus-switch coding for reducing power dissipation in off-chip buses.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan	A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Jihong Ren, Mark R. Greenstreet	Crosstalk Cancellation for Realistic PCB Buses.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Andersson, Atila Alvandpour, Christer Svensson	An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Maged Ghoneima, Yehea I. Ismail	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, interconnects, buses, coupling capacitance
2	Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy	Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses.	ISLPED	2004	DBLP DOI BibTeX RDF
2	Jacob Löfvenberg	Non-Redundant Coding for Deep Sub-Micron Address Buses.	IWSOC	2004	DBLP DOI BibTeX RDF
2	Tina Lindkvist, Jacob Löfvenberg, Henrik Ohlsson, Kenny Johansson, Lars Wanhammar	A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances.	IWSOC	2004	DBLP DOI BibTeX RDF
2	Ibrahim M. Elfadel, Alina Deutsch, Gerard V. Kopcsay, Bradley Rubin, Howard Smith	A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.	DATE	2004	DBLP DOI BibTeX RDF
2	Claudia Kretzschmar, André K. Nieuwland, Dietmar Müller	Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work.	DATE	2004	DBLP DOI BibTeX RDF
2	Susumu Matsumae	Optimal Simulation of Meshes with Dynamically Separable Buses by Meshes with Statically Partitioned Buses.	ISPAN	2004	DBLP DOI BibTeX RDF
2	Victor Wen, Mark Whitney, Yatish Patel, John Kubiatowicz	Exploiting Prediction to Reduce Power on Buses.	HPCA	2004	DBLP DOI BibTeX RDF
2	Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag	Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses.	ICCD	2004	DBLP DOI BibTeX RDF
2	Andrew Tjang, Michael Pagliorola, Hiral Patel, Xiaoyan Li, Richard P. Martin	Active Tapes: Bus-Based Sensor Networks.	LCN	2004	DBLP DOI BibTeX RDF	Power buses, Data buses, Sensor networks
2	Amos Beimel, Shlomi Dolev	Buses for Anonymous Message Delivery.	J. Cryptology	2003	DBLP DOI BibTeX RDF	Privacy, Traffic analysis, Anonymous communication
2	Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf	A dictionary-based en/decoding scheme for low-power data buses.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Dinesh C. Suresh, Jun Yang 0002, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar	FV-MSB: A Scheme for Reducing Transition Activity on Data Buses.	HiPC	2003	DBLP DOI BibTeX RDF
2	Jiangjiang Liu, Nihar R. Mahapatra, Krishnan Sundaresan	Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses.	ISVLSI	2003	DBLP DOI BibTeX RDF
2	Sampo Tuuna, Jouni Isoaho	Estimation of Crosstalk Noise for On-Chip Buses.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato	An evolutionary approach for reducing the energy in address buses.	ISICT	2003	DBLP DOI BibTeX RDF
2	Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura	A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits.	DSD	2003	DBLP DOI BibTeX RDF
2	Enrico Macii, Massimo Poncino, Sabino Salerno	Combining wire swapping and spacing for low-power deep-submicron buses.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	low-power design, physical design, crosstalk, bus encoding
2	Susumu Matsumae	An Efficient Scaling-Simulation Algorithm of Reconfigurable Meshes by Meshes with Partitioned Buses.	IPDPS	2003	DBLP DOI BibTeX RDF
2	Susumu Matsumae	Simulation of Meshes with Separable Buses by Meshes with Multiple Partitioned Buses.	IPDPS	2003	DBLP DOI BibTeX RDF
2	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan	Power efficient encoding techniques for off-chip data buses.	CASES	2003	DBLP DOI BibTeX RDF	FV, FV-MSB-LSB, data bus, low power, bus encoding