Search results for "cache"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau	Reducing memory latency using a small software driven array cache.	HICSS	1995	DBLP DOI BibTeX RDF	small software driven array cache, data references, array reference, nonarray reference, data cache designs, cache space, cache control mechanisms, array references, data cache performance, hardware driven data prefetching scheme, software driven cache design, array cache, low runtime overhead, performance evaluation, data structures, compiler, programming, programming, prefetching, program compilers, cache storage, cache performance, temporal locality, spatial locality, memory latency
10	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
8	Frank Mueller, David B. Whalley	Fast instruction cache analysis via static cache simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	instruction cache analysis, static cache simulation, cache configuration, instruction reference, cache hit, counter incrementation, code execution frequency, local state information updating, frequency counters, program exit, virtual machines, cache storage, program diagnostics, dynamic simulation, cache miss
7	Prateek Pujara, Aneesh Aggarwal	Increasing cache capacity through word filtering.	ICS	2007	DBLP DOI BibTeX RDF	cache capacity, cache compression, cache noise, cache organization, cache miss rate
7	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
7	José V. Busquets-Mataix, Juan José Serrano	The impact of extrinsic cache performance on predictability of real-time systems.	RTCSA	1995	DBLP DOI BibTeX RDF	tighter bounds, cached programs, extrinsic cache behavior, inter-task cache interference, cache predictability, performance evaluation, real-time systems, real-time systems, predictability, worst case execution time, schedulability analysis, cache storage, cache performance
7	Bob Janssens, W. Kent Fuchs	The Performance of Cache-Based Error Recovery in Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	cache-based error recovery performance, cache-based checkpointing, rollback error recovery, shared-memorymultiprocessors, inherent redundancy, computation state, rollback propagation, EncoreMultimax, recovery schemes, cache-based schemes, low performance overhead, checkpoint interval, performance evaluation, performance evaluation, virtual machines, multiprocessors, redundancy, memory hierarchy, shared memory systems, system recovery, buffer storage, parallel applications, cache coherence protocol, transient errors, cache replacement policy, address traces
6	Mazen Kharbutli, Yan Solihin	Counter-Based Cache Replacement and Bypassing Algorithms.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Cache Bypassing, Counter-Based Algorithms, Cache memories, Cache Replacement, Cache Misses
6	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	Fast configurable-cache tuning with a unified second-level cache.	ISLPED	2005	DBLP DOI BibTeX RDF	cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache
6	Aviral Shrivastava, Ilya Issenin, Nikil Dutt	Compilation techniques for energy reduction in horizontally partitioned cache architectures.	CASES	2005	DBLP DOI BibTeX RDF	XScale, horizontally-partitioned cache, mini-cache, split cache, compiler, energy, data cache
6	Mark Brehob, Stephen Wagner, Eric Torng, Richard J. Enbody	Optimal Replacement Is NP-Hard for Nonstandard Caches.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	optimal cache replacement policy, interval scheduling, skew cache, multilateral cache, approximation algorithm, Cache, victim cache
6	Johnson Kin, Munish Gupta, William H. Mangione-Smith	The Filter Cache: An Energy Efficient Memory Structure.	MICRO	1997	DBLP BibTeX RDF	direct mapped 256-byte filter cache, energy efficient memory structure, on-chip caches, static RAM, microprocessors, microprocessor chips, power reduction, embedded applications, L2 cache, filter cache, L1 cache
6	Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe	Cache modeling for real-time software: beyond direct mapped instruction caches. (PDF / PS)	IEEE Real-Time Systems Symposium	1996	DBLP DOI BibTeX RDF	direct mapped instruction caches, worst case timing analysis, cache hits, set associative instruction caches, unified caches, cinderella, research, integer-linear-programming, worst case execution time, data caches, cache storage, design tool, memory performance, cache misses, real-time software, tight bound, cache modeling, hardware system
6	Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King	Performance of Shared Cache on Multithreaded Architectures.	PDP	1996	DBLP DOI BibTeX RDF	shared cache performance, trace-driven simulation technique, storage hierarchy system, multithreaded execution environment, multithread scheduling techniques, server/workstation workload mix, MRU priority scheduling scheme, round-robin scheduling method, absolute hit ratio, concurrent threads, simulation, performance evaluation, parallel architectures, shared memory systems, processor scheduling, cache storage, multithreaded architectures, program traces, set associativity, cache size, direct-map cache
6	Sreeram Duvvuru, Siamak Arya	Evaluation of a branch target address cache.	HICSS	1995	DBLP DOI BibTeX RDF	branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes
6	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
6	Wesley K. Kaplow, William Maniatty, Boleslaw K. Szymanski	Impact of memory hierarchy on program partitioning and scheduling.	HICSS	1995	DBLP DOI BibTeX RDF	parallel program scheduling, nonlinear cache-miss rates, loop nest execution simulation, architecturally parameterized cache simulator, loop range, cache-miss ratio, loop interchange, iteration-space blocking, program runtime estimation, IBM 9076 SP1, SuperSPARC, scheduling, parallel programming, optimisation, memory hierarchy, processor scheduling, software performance evaluation, memory architecture, cache storage, program optimization, cache performance, program control structures, program partitioning, Intel i860
6	Scott D. Carson, Sanjeev Setia	Analysis of the Periodic Update Write Policy For Disk Cache.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	periodic update write policy, average access time, dirty cache blocks, disk read requests, cache-hit ratio, competing cache write policies, bulk arrivals, traffic jam effect, degraded service, write packages, scheduling, file systems, storage management, buffer storage, storage allocation, disk scheduling, data storage, computer systems, disk cache, design criteria, average response time
5	Mirza Beg, Peter van Beek	A graph theoretic approach to cache-conscious placement of data for direct mapped caches.	ISMM	2010	DBLP DOI BibTeX RDF	cache consciousness, data placement in cache, offline algorithms, memory management, cache optimization
5	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).	CASES	2009	DBLP DOI BibTeX RDF	low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs
5	David K. Tam, Reza Azimi, Livio Soares, Michael Stumm	RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations.	ASPLOS	2009	DBLP DOI BibTeX RDF	miss rate curve, performance monitoring unit, shared cache management, chip multiprocessor, dynamic optimization, multicore processor, shared cache, cache management, cache partitioning, hardware performance counters, online optimization
5	Rezaul Alam Chowdhury, Vijaya Ramachandran	Cache-efficient dynamic programming algorithms for multicores.	SPAA	2008	DBLP DOI BibTeX RDF	parallelism, multicore, shared cache, distributed cache, cache-efficiency
5	Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle	IATAC: a smart predictor to turn-off L2 cache lines.	TACO	2005	DBLP DOI BibTeX RDF	turning off cache lines, low power, Cache memories, L2 cache
5	Afrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany	Improving data cache performance with integrated use of split caches, victim cache and stream buffers.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF	array cache, memory access time, scalar cache, victim cache, stream buffer
5	Jih-Fu Tu	Cache Management for Discrete Processor Architectures.	ISPA	2005	DBLP DOI BibTeX RDF	Discrete processor architectures, write-invalidate (WI) and cache block, multithreading, cache coherency, shared cache, memory latency
5	Rong Xu, Zhiyuan Li	A sample-based cache mapping scheme.	LCTES	2005	DBLP DOI BibTeX RDF	cache bypass, cache mapping, mini cache, trace sampling, profiling, handheld devices
5	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
5	Ann Gordon-Ross, Frank Vahid, Nikil Dutt	A first look at the interplay of code reordering and configurable caches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	cache exploration, code reorganization, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache, code layout, code reordering
5	Ann Gordon-Ross, Frank Vahid, Nikil Dutt	Automatic Tuning of Two-Level Caches to Embedded Applications.	DATE	2004	DBLP DOI BibTeX RDF	cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, Configurable cache
5	Jamison D. Collins, Dean M. Tullsen	Runtime identification of cache conflict misses: The adaptive miss buffer.	ACM Trans. Comput. Syst.	2001	DBLP DOI BibTeX RDF	adaptive miss buffer, cache exclusion, prefetching, victim cache, Cache architecture, conflict misses
5	Chih-Yung Chang, Jang-Ping Sheu, Hsi-Chiuen Chen	Reducing Cache Conflicts by Multi-Level Cache Partitioning and Array Elements Mapping. (PDF / PS)	ICPADS	2000	DBLP DOI BibTeX RDF	array padding, multi-level cache, cache partitioning, loop tiling, direct mapping, cache conflict
5	Teresa L. Johnson, Daniel A. Connors, Matthew C. Merten, Wen-mei W. Hwu	Run-Time Cache Bypassing.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	cache bypassing, Data cache, cache management, temporal locality, spatial locality
5	Jih-Kwon Peir, Windsor W. Hsu, Alan Jay Smith	Functional Implementation Techniques for CPU Cache Memories.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	cache access mechanism, cache area and bandwidth, Cache memory, address translation
5	Trishul M. Chilimbi, Mark D. Hill, James R. Larus	Cache-Conscious Structure Layout.	PLDI	1999	DBLP DOI BibTeX RDF	cache-conscious allocation, cache-conscious data placement, cache-conscious reorganization, clustering, coloring
5	David C. Wong, Edward W. Davis, Jeffrey O. Young	A Software Approach to Avoiding Spatial Cache Collisions in Parallel Processor Systems.	IEEE Trans. Parallel Distrib. Syst.	1998	DBLP DOI BibTeX RDF	Cache collision, cache offset, highly parallel systems, sequential DO-loops, direct-mapped cache
5	Nigel P. Topham, Antonio González, José González	The Design and Performance of a Conflict-Avoiding Cache.	MICRO	1997	DBLP BibTeX RDF	cache architecture design, conflict miss ratios, conflict-avoiding cache performance, data access cost minimization, high performance architectures, multi-level memory hierarchies, polynomial modulus functions, cache storage, main memory
5	Jonas Skeppstedt, Michel Dubois	Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	hybrid compiler/hardware prefetching, low-overhead cache miss traps, data prefetching technique, cache coherent multiprocessors, cache miss traps, trap handler, simulated multiprocessor, compiler, multiprocessors, multiprocessing systems
5	Masaki Aida, Noriyuki Takahashi	Evaluation of the number of destination hosts for data networking and its application to address cache design.	ICCCN	1997	DBLP DOI BibTeX RDF	destination hosts, address cache design, address cache tables capacity, large-scale computer communication networks, packet destination addresses, cache hit probability, aging algorithm, probability, Zipf's law, data networking
5	Gabriele Luculli, Marco Di Natale	A cache-aware scheduling algorithm for embedded systems. (PDF / PS)	IEEE Real-Time Systems Symposium	1997	DBLP DOI BibTeX RDF	cache aware scheduling algorithm, task layout, static systems, cache miss costs, normal execution time, time driven dispatching, application tasks, pre defined sequence, optimal cache sequencing, simulated annealing techniques, real-time systems, embedded systems, execution time, computation time, instruction caching, real time task scheduling, scheduling model
5	Dimitrios Stiliadis, Anujan Varma	Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	data cache, instruction cache, cache simulation, Victim cache, direct-mapped cache
5	Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura	An Optical Bus Computer Cluster with a deferred cache coherence protocol. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	Optical Bus Computer Cluster, deferred cache coherence protocol, optical star-coupler, one-hop simultaneous broadcasting, wavelength multiplexing, deferred cache coherence, coherence maintenance, protocols, wavelength-division multiplexing, optical interconnections, cache storage
5	Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh	The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention
5	Chi-Hung Chi, Siu-Chung Lau	Reducing data access penalty using intelligent opcode-driven cache prefetching. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	data access penalty, intelligent opcode-driven, LOAD-UPDATE, LOAD-MODIFY, IBM PowerPC, HP Precision Architecture, intelligent data prefetching, instruction decode unit, storage management, data cache, cache storage, cache prefetching
5	Ricardo Bianchini, Leonidas I. Kontothanassis	Algorithms for categorizing multiprocessor communication under invalidate and update-based coherence protocols.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	shared-memory multiprocessor communication, invalidate-based cache coherence protocols, update-based cache coherence protocols, reference patterns, sharing patterns, useless data traffic, data traffic categorization, parallel programming, parallel programs, virtual machines, transaction processing, shared memory systems, coherence, cache storage, telecommunication traffic, cache misses, simulation algorithms, update transactions, memory protocols
5	Qing Yang	Introducing a New Cache Design into Vector Computers.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	prime-mapped cache, cache miss ratio, speed gap, memory architecture, buffer storage, cache design, performance gains, vector processor systems, Mersenne prime, cache organizations, vector computers
5	Qing Yang, George Thangadurai, Laxmi N. Bhuyan	Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	adaptive cache coherence protocol, cache-based multiprocessor, cache coherence scheme, memoryarchitecture, protocols, multiprocessor interconnection networks, multistage interconnection network, buffer storage, hierarchical network
5	Dominique Thiébaut, Harold S. Stone	Improving Disk Cache Hit-Ratios Through Cache Partitioning.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	fully associative cache memories, buffer storage, adaptive algorithm, cache storage, content-addressable storage, cache partitioning, magnetic disc storage, hit-ratios, disk cache, queuing network model
4	Izuchukwu Nwachukwu, Krishna Kavi, Fawibe Ademola, Chris Yan	Evaluation of Techniques to Improve Cache Access Uniformities.	ICPP	2011	DBLP DOI BibTeX RDF	Cache Indexing, Non-Uniformity of Cache Accesses, Cache Memories, Performance Improvement
4	Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John	The virtual write queue: coordinating DRAM and last-level cache policies.	ISCA	2010	DBLP DOI BibTeX RDF	cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
4	Young Jin Park, Hong Jun Choi, Cheol Hong Kim, Jong-Myon Kim	Energy-aware Filter Cache Architecture for Multicore Processors.	DELTA	2010	DBLP DOI BibTeX RDF	energy consumption, multicore processor, instruction cache, victim cache, filter cache
4	Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Xuehai Zhou, Edwin Hsing-Mean Sha	Write activity reduction on flash main memory via smart victim cache.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	cache, nand flash memory, main memory, victim cache
4	Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran	SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.	DAC	2010	DBLP DOI BibTeX RDF	miss rate, simulation, round robin, cache simulation, L1 cache
4	Guangdeng Liao, Heeyeol Yu, Laxmi N. Bhuyan	A new IP lookup cache for high performance IP routers.	DAC	2010	DBLP DOI BibTeX RDF	cache indexing, cache replacement policies, IP routers
4	Yun Liang, Tulika Mitra	Instruction cache locking using temporal reuse profile.	DAC	2010	DBLP DOI BibTeX RDF	cache locking, temporal reuse profile, cache
4	Sorin Faibish, Peter Bixby, John Forecast, Philippe Armangau, Sitaram Pawar	A new approach to file system cache writeback of application data.	SYSTOR	2010	DBLP DOI BibTeX RDF	cache writeback, dirty pages, rate flushing, watermark flushing, feedback loop, buffer cache
4	Deng Yadan, Jing Ning, Xiong Wei, Chen Luo, Chen Hongsheng	Hash Join Optimization Based on Shared Cache Chip Multi-processor.	DASFAA	2009	DBLP DOI BibTeX RDF	Radix-Join, Shared L2-Cache, Chip Multi-Processor, Cache Conflict
4	Jongmin Lee 0002, Soontae Kim	An energy-delay efficient 2-level data cache architecture for embedded system.	ISLPED	2009	DBLP DOI BibTeX RDF	2-level data cache, early cache hit predictor, one-way write
4	Chenjie Yu, Xiangrong Zhou, Peter Petrov	Low-power inter-core communication through cache partitioning in embedded multiprocessors.	SBCCI	2009	DBLP DOI BibTeX RDF	low-power cache architectures, low-power cache coherence, MPSoC, on-chip communication
4	Jinglei Wang, Dongsheng Wang, Yibo Xue, Haixia Wang	An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
4	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
4	Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran	SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	miss rate, simulation, LRU, cache simulation, L1 cache
4	Bingsheng He, Qiong Luo	Cache-oblivious databases: Limitations and opportunities.	ACM Trans. Database Syst.	2008	DBLP DOI BibTeX RDF	cache-conscious, chip multiprocessors, data caches, simultaneous multithreading, Cache-oblivious
4	Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid	A table-based method for single-pass cache optimization.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	configurable cache tuning, low energy, cache optimization
4	Roberto Giorgi, Paolo Bennati	Filtering drowsy instruction cache to achieve better efficiency.	SAC	2008	DBLP DOI BibTeX RDF	low-power, leakage, drowsy cache, filter cache
4	Clément Ballabriga, Hugues Cassé, Pascal Sainrat	An improved approach for set-associative instruction cache partial analysis.	SAC	2008	DBLP DOI BibTeX RDF	WCET computation, partial cache analysis, partial static analysis, abstract interpretation, COTS, instruction cache
4	Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou	Deconstructing new cache designs for thwarting software cache-based side channel attacks.	CSAW	2008	DBLP DOI BibTeX RDF	microarchitectural analysis, cryptanalysis, side-channel analysis, timing attack, cache architecture, cache attack
4	Vivy Suhendra, Tulika Mitra	Exploring locking & partitioning for predictable shared caches on multi-cores.	DAC	2008	DBLP DOI BibTeX RDF	cache locking, shared-cache multi-core, WCET, cache partitioning
4	Mohsen Sharifi, Behrouz Zolfaghari	YAARC: yet another approach to further reducing the rate of conflict misses.	The Journal of Supercomputing	2008	DBLP DOI BibTeX RDF	Skewed associative cache, YAARC cache, Hit rate, Cache, Conflict misses
4	Jan Reineke, Daniel Grund, Christoph Berg, Reinhard Wilhelm	Timing predictability of cache replacement policies.	Real-Time Systems	2007	DBLP DOI BibTeX RDF	Predictability, Timing analysis, Hard real-time systems, Cache replacement policies, Cache analysis
4	Michael Behar, Avi Mendelson, Avinoam Kolodny	Trace cache sampling filter.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	cache utilization, sampling filter, power dissipation, Trace cache
4	Xudong Shi, Feiqi Su, Jih-Kwon Peir, Ye Xia 0001, Zhen Yang	Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility.	ISPASS	2007	DBLP DOI BibTeX RDF	multiple cache organization, single-pass simulation, on-chip storage space, on-chip cache capacity, single-pass stack simulation, global stack, shared stack, per-core private stack, single simulation pass, average memory access time, chip-multiprocessor, data replication, data accessibility, abstract model, reuse distances
4	Yang Li, Lin Zuo, Jun Wei, Hua Zhong, Tao Huang	Sequential Pattern-Based Cache Replacement in Servlet Container.	ICWE	2007	DBLP DOI BibTeX RDF	Servlet Cache, Sequential Patterns, Cache Replacement
4	Wenzhong Li, Edward Chan, Yilin Wang, Daoxu Chen	Cache Invalidation Strategies for Mobile Ad Hoc Networks.	ICPP	2007	DBLP DOI BibTeX RDF	Cache invalidation strategies, Mobile computing, Mobile ad hoc network, Performance analysis, Cache consistency
4	Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Shobhit O. Kanaujia	Compression in cache design.	ICS	2007	DBLP DOI BibTeX RDF	cache compression, prefetching, cache design
4	Kamen Yotov, Thomas Roeder, Keshav Pingali, John A. Gunnels, Fred G. Gustavson	An experimental comparison of cache-oblivious and cache-conscious programs.	SPAA	2007	DBLP DOI BibTeX RDF	cache-conscious algorithms, memory hierarchy, memory bandwidth, memory latency, numerical software, cache-oblivious algorithms
4	Yu Huang 0002, Beihong Jin, Jiannong Cao, Guangzhong Sun, Yulin Feng	A Selective Push Algorithm for Cooperative Cache Consistency Maintenance over MANETs.	EUC	2007	DBLP DOI BibTeX RDF	Cache Status Maintenance, Selective Push, Mobile Ad hoc Networks, Stateful, Cooperative Caching, Cache Consistency
4	Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke	Compiler-managed partitioned data caches for low power.	LCTES	2007	DBLP DOI BibTeX RDF	hardware/software co-managed cache, instruction-driven cache management, partitioned cache, low-power, embedded processor
4	Yefim Shuf, Ian M. Steiner	Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations.	ISPASS	2007	DBLP DOI BibTeX RDF	J2EE workload, Java benchmarks, SPECjvm98, SPECjbb2000, Java 2 Enterprise Edition, SPECjAppServer2004, systems research, software research, cache-to-cache modified data transfers, intelligent thread co-scheduling, Java heap, bursty data cache, Java virtual method calls, optimizations, performance analysis, garbage collection, instruction cache, data prefetching, commercial workload
4	Yingwu Zhu, Yiming Hu	Exploiting client caches to build large Web caches.	The Journal of Supercomputing	2007	DBLP DOI BibTeX RDF	Hier-GD, Client cache, Latency gain, Infinite cache size, Cooperative proxy caching, Peer-to-peer, Proxy cache
4	Bingsheng He, Qiong Luo, Byron Choi	Cache-Conscious Automata for XML Filtering.	IEEE Trans. Knowl. Data Eng.	2006	DBLP DOI BibTeX RDF	Cache-conscious, XML filtering, cache behavior model, query processing, automata, buffer
4	Stavros Harizopoulos, Anastassia Ailamaki	Improving instruction cache performance in OLTP.	ACM Trans. Database Syst.	2006	DBLP DOI BibTeX RDF	Instruction cache, cache misses
4	Abu Asaduzzaman, Imad Mahgoub	Cache modeling and optimization for portable devices running MPEG-4 video decoder.	Multimedia Tools Appl.	2006	DBLP DOI BibTeX RDF	MPEG-4, Cache optimization, Portable devices, Cache modeling, Video decoder
4	Ke Meng, Russ Joseph	Process variation aware cache leakage management.	ISLPED	2006	DBLP DOI BibTeX RDF	gated-VDD, selective cache ways, low power, process variation, leakage, cache management
4	Sung Woo Chung, Kevin Skadron	Using Branch Prediction Information for Near-Optimal I-Cache Leakage.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low Power, Branch Prediction, Leakage, Instruction Cache, Drowsy Cache
4	Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid	Configurable cache subsetting for fast cache tuning.	DAC	2006	DBLP DOI BibTeX RDF	configurable cache tuning, low energy, cache optimization
4	Alberto Ros, Manuel E. Acacio, José M. García	An efficient cache design for scalable glueless shared-memory multiprocessors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	L2, directory structure, glueless shared-memory multiprocessors, cache, cache coherence, memory wall
4	Liangzhong Yin, Guohong Cao	Supporting Cooperative Caching in Ad Hoc Networks.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	simulations, ad hoc networks, data dissemination, Cooperative cache, cache management, cache replacement policy
4	Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Analyzing data reuse for cache reconfiguration.	ACM Trans. Embedded Comput. Syst.	2005	DBLP DOI BibTeX RDF	cache polymorphism, compilers, energy consumption, Embedded software, data reuse, cache locality
4	Wei Zhang	Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	write-back cache, in-cache replication, Soft error
4	Mazen Kharbutli, Yan Solihin, Jaejin Lee	Eliminating Conflict Misses Using Prime Number-Based Cache Indexing.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Cache hashing, cache indexing, prime modulo, odd-multiplier displacement, conflict misses
4	Josef Weidendorfer, Carsten Trinitis	Collecting and Exploiting Cache-Reuse Metrics.	International Conference on Computational Science	2005	DBLP DOI BibTeX RDF	Cache Reuse Metrics, Profiling, Cache Simulation
4	Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA substrate for flexible CMP cache sharing.	ICS	2005	DBLP DOI BibTeX RDF	cache sharing, non-uniform cache architecture, chip-multiprocessor
4	Aneesh Aggarwal	Reducing latencies of pipelined cache accesses through set prediction.	ICS	2005	DBLP DOI BibTeX RDF	instructions per cycle, line prediction, set prediction, speculative cache access, cache memory
4	Yaomin Fu, Peter Bodorik, Dawn N. Jutla	A Self-Managed Predicate-Based Cache.	CNSR	2005	DBLP DOI BibTeX RDF	Predicate Cache, Cache Evaluation, Distributed Systems, Storage Management
4	Soong Hyun Shin, Cheol Hong Kim, Chu Shik Jhon	An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information.	EUC	2005	DBLP DOI BibTeX RDF	Computer architecture, embedded processor, instruction cache, cache prefetching
4	Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri, Matteo Monchiero, Gianluca Palermo	AES Power Attack Based on Induced Cache Miss and Countermeasure.	ITCC	2005	DBLP DOI BibTeX RDF	Cache, Block Cipher, AES, Power Analysis, Cache Miss
4	Janis Sermulins, William Thies, Rodric M. Rabbah, Saman P. Amarasinghe	Cache aware optimization of stream programs.	LCTES	2005	DBLP DOI BibTeX RDF	cache, embedded, fusion, cache optimizations, synchronous dataflow, stream programing, StreamIt
4	Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke	Automated data cache placement for embedded VLIW ASIPs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	cache, ASIP, cache optimization, embedded applications
4	Jianliang Xu, Qinglong Hu, Wang-Chien Lee, Dik Lun Lee	Performance Evaluation of an Optimal Cache Replacement Policy for Wireless Data Dissemination.	IEEE Trans. Knowl. Data Eng.	2004	DBLP DOI BibTeX RDF	wireless data dissemination, mobile computing, performance analysis, data management, Cache replacement, cache consistency
4	Joon-Sang Park, Michael Penner, Viktor K. Prasanna	Optimizing Graph Algorithms for Improved Cache Performance.	IEEE Trans. Parallel Distrib. Syst.	2004	DBLP DOI BibTeX RDF	Cache-friendly algorithms, shortest path, graph algorithms, minimum spanning trees, graph matching, algorithm performance, cache-oblivious algorithms, data layout optimizations