Search results for "cache coherence protocol"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Thuy Duong Vu, Li Zhang, Chris R. Jesshope	The Verification of the On-Chip COMA Cache Coherence Protocol.	AMAST	2008	DBLP DOI BibTeX RDF	on-chip COMA cache coherence protocol, location consistency, verification, Abstract State Machine
3	Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura	An Optical Bus Computer Cluster with a deferred cache coherence protocol. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	Optical Bus Computer Cluster, deferred cache coherence protocol, optical star-coupler, one-hop simultaneous broadcasting, wavelength multiplexing, deferred cache coherence, coherence maintenance, protocols, wavelength-division multiplexing, optical interconnections, cache storage
2	Bo Zhang, Binoy Ravindran	Brief Announcement: Relay: A Cache-Coherence Protocol for Distributed Transactional Memory.	OPODIS	2009	DBLP DOI BibTeX RDF
2	Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal	A tuneable software cache coherence protocol for heterogeneous MPSoCs.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	performance, design, reliability
2	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato	Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF
2	Hongbo Zeng, Jun Wang, Ge Zhang, Weiwu Hu	An interconnect-aware power efficient cache coherence protocol for CMPs.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato	A fault-tolerant directory-based cache coherence protocol for CMP architectures.	DSN	2008	DBLP DOI BibTeX RDF
2	Rana Ejaz Ahmed	Energy-Aware Cache Coherence Protocol for Chip-Multiprocessors.	CCECE	2006	DBLP DOI BibTeX RDF
2	Nirav Dave, Man Cheuk Ng, Arvind	Automatic synthesis of cache-coherence protocol processors using Bluespec.	MEMOCODE	2005	DBLP DOI BibTeX RDF
2	Félix García Carballeira, Jesús Carretero, Alejandro Calderón, José María Pérez, José Daniel García	An Adaptive Cache Coherence Protocol Specification for Parallel Input/Output Systems.	IEEE Trans. Parallel Distrib. Syst.	2004	DBLP DOI BibTeX RDF
2	Ying Chen, Dennis Abts, David J. Lilja	State Pruning for Test Vector Generation for a Multiprocessor Cache Coherence Protocol.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
2	Anca-Andreea Ivan, Vijay Karamcheti	Flecc: A Flexible Cache Coherence Protocol for Dynamic Component-Based Systems.	IPDPS	2004	DBLP DOI BibTeX RDF
2	Daehyun Kim, Mainak Chaudhuri, Mark Heinrich, Evan Speight	Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Active memory systems, address remapping, flexible memory controller architecture, distributed shared memory, cache coherence protocol
2	Jun Pang, Wan Fokkink, Rutger F. H. Hofman, Ronald Veldema	Model Checking a Cache Coherence Protocol for a Java DSM Implementation.	IPDPS	2003	DBLP DOI BibTeX RDF	µCRL, Java, model checking, distributed shared memory, cache coherence protocols
2	Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood	Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	multicast snooping, Cache coherence, protocol verification, protocol specification, memory consistency
2	Kai Baukus, Yassine Lakhnech, Karsten Stahl	Parameterized Verification of a Cache Coherence Protocol: Safety and Liveness.	VMCAI	2002	DBLP DOI BibTeX RDF
2	Kenneth L. McMillan	Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking.	CHARME	2001	DBLP DOI BibTeX RDF
2	Srivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini, Adnan Aziz, Lizy Kurian John	Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking.	VLSI Design	1999	DBLP DOI BibTeX RDF
2	Won-Kee Hong, Nam-Hee Kim, Shin-Dug Kim	Design and Performance Evaluation of an Adaptive Cache Coherence Protocol. (PDF / PS)	ICPADS	1998	DBLP DOI BibTeX RDF
2	John Heinlein, Kourosh Gharachorloo, Robert P. Bosch Jr., Mendel Rosenblum, Anoop Gupta	Coherent Block Data Transfer in the FLASH Multiprocessor. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	FLASH multiprocessor, block data transfer, multiple communication protocols, embedded protocol processor, protocol, shared memory, prefetching, cache storage, FLASH, cache coherence protocol, multiprocessor architecture, MAGIC
2	Rong-Yuh Hwang	An Efficient Technique of Instruction Scheduling on a Superscalar-Based Mulprocessor. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	FLASH multiprocessor, block data transfer, multiple communication protocols, embedded protocol processor, protocol, shared memory, prefetching, cache storage, FLASH, cache coherence protocol, multiprocessor architecture, MAGIC
2	Masaru Takesue	A tampering protocol for reducing the coherence transactions in regular computation.	ISPAN	1997	DBLP DOI BibTeX RDF	tampering protocol, coherence transactions, regular computation, latency of communication, protocols, multiprocessor, cache-coherence protocol, RTL simulator
2	Kazuki Joe, Akira Fukuda	Applying the Semi-Markov Memory and Cache Coherence Interference Model to an Updating Based Cache Coherence Protocol.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
2	Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki	A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor.	HPCA	1996	DBLP DOI BibTeX RDF
2	Bob Janssens, W. Kent Fuchs	The Performance of Cache-Based Error Recovery in Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	cache-based error recovery performance, cache-based checkpointing, rollback error recovery, shared-memorymultiprocessors, inherent redundancy, computation state, rollback propagation, EncoreMultimax, recovery schemes, cache-based schemes, low performance overhead, checkpoint interval, performance evaluation, performance evaluation, virtual machines, multiprocessors, redundancy, memory hierarchy, shared memory systems, system recovery, buffer storage, parallel applications, cache coherence protocol, transient errors, cache replacement policy, address traces
2	Qing Yang, George Thangadurai, Laxmi N. Bhuyan	Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	adaptive cache coherence protocol, cache-based multiprocessor, cache coherence scheme, memoryarchitecture, protocols, multiprocessor interconnection networks, multistage interconnection network, buffer storage, hierarchical network
2	Mazin S. Algudady, Chita R. Das, Matthew Thazhuthaveetil	A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches.	SC	1990	DBLP BibTeX RDF
2	Claude Girault, C. Chatelain, Serge Haddad	Specification and properties of a cache coherence protocol model.	European Workshop on Applications and Theory of Petri Nets	1986	DBLP DOI BibTeX RDF	verification, Petri nets, protocols, specification, multiprocessors, memory hierarchy, cache coherence
1	Shuchang Shan, Yu Hu, Xiaowei Li	Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors.	DSN	2011	DBLP DOI BibTeX RDF
1	Xin Lai, Cong Liu, Zhiying Wang	Applying Formal Verification to a Cache Coherence Protocol in TLS.	EMS	2011	DBLP DOI BibTeX RDF
1	Yi Xu, Yu Du, Youtao Zhang, Jun Yang 0002	A composite and scalable cache coherence protocol for large scale CMPs.	ICS	2011	DBLP DOI BibTeX RDF
1	Rana E. Ahmed, Muhammad K. Dhodhi	Directory-based cache coherence protocol for power-aware chip-multiprocessors.	CCECE	2011	DBLP DOI BibTeX RDF
1	Fucen Zeng, Lin Qiao, Wei Wang	PEPCP: A Power-Efficient Parallel Coherence Protocol for Large-Scale Network-on-Chip.	ICPP	2011	DBLP DOI BibTeX RDF	Network on chip, chip multiprocessors, cache coherence protocol
1	Bo Zhang, Binoy Ravindran	Dynamic analysis of the relay cache-coherence protocol for distributed transactional memory.	IPDPS	2010	DBLP DOI BibTeX RDF
1	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Tiled chip multiprocessor, heterogeneous on-chip interconnection network, cache coherence protocol, energy-efficient architectures, parallel scientific applications
1	Alberto Ros, Manuel E. Acacio, José M. García	A Direct Coherence Protocol for Many-Core Chip Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2010	DBLP DOI BibTeX RDF	Many-core CMP, direct coherence, indirection problem, on-chip network traffic, cache coherence protocol
1	Jungwoo Ha, Stephen P. Crago	Opportunities for concurrent dynamic analysis with explicit inter-core communication.	PASTE	2010	DBLP DOI BibTeX RDF	inter-core communication, concurrency, dynamic analysis, instrumentation
1	Bo Zhang, Binoy Ravindran	Brief announcement: queuing or priority queuing? on the design of cache-coherence protocols for distributed transactional memory.	PODC	2010	DBLP DOI BibTeX RDF	distributed queuing, transactional memory, cache-coherence protocols
1	Fei Cao, Zhiyong Liu	Snooping and Ordering Ring - An Efficient Cache Coherence Protocol for Ring Connected CMP.	ICPADS	2009	DBLP DOI BibTeX RDF
1	Jinglei Wang, Dongsheng Wang, Yibo Xue, Haixia Wang	An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
1	Paul E. West, Yuval Peress, Gary S. Tyson, Sally A. McKee	Core monitors: monitoring performance in multicore processors.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	scheduling, debugging, profiling, multicore, cache coherency, performance monitoring, realtime
1	Colin Blundell, Milo M. K. Martin, Thomas F. Wenisch	InvisiFence: performance-transparent memory ordering in conventional multiprocessors.	ISCA	2009	DBLP DOI BibTeX RDF	parallel programming, memory consistency
1	Abdullah Muzahid, Darío Suárez Gracia, Shanxiang Qi, Josep Torrellas	SigRace: signature-based data race detection.	ISCA	2009	DBLP DOI BibTeX RDF	SigRace, concurrency defect, signature, timestamp, data race, happened-before
1	Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	In-network coherence filtering: snoopy coherence without broadcasts.	MICRO	2009	DBLP DOI BibTeX RDF
1	Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai	Architecting a chunk-based memory race recorder in modern CMPs.	MICRO	2009	DBLP DOI BibTeX RDF	memory race recorder, determinism, deterministic replay
1	Jesse D. Bingham, John Erickson, Gaurav Singh, Flemming Andersen	Industrial strength refinement checking.	FMCAD	2009	DBLP DOI BibTeX RDF
1	Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects.	HPCA	2009	DBLP DOI BibTeX RDF
1	Huandong Wang, Dan Tang, Xiang Gao, Yunji Chen	An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP.	NAS	2009	DBLP DOI BibTeX RDF
1	Alberto Ros, Manuel E. Acacio, José M. García	Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs.	APPT	2009	DBLP DOI BibTeX RDF
1	Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne	MPSoC Design Using Application-Specific Architecturally Visible Communication.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Zheng Chen, Yin-Liang Zhao, Xiao-Yu Pan, Zhao-Yu Dong, Bing Gao, Zhi-Wen Zhong	An Overview of Prophet.	ICA3PP	2009	DBLP DOI BibTeX RDF	Thread partitioning, Pre-computation slice, Speculative Multithreading Architecture, Thread level parallelism, Speculative multithreading
1	Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee	Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors
1	Alberto Ros, Manuel E. Acacio, José M. García	DiCo-CMP: Efficient cache coherency in tiled CMP architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Blas Cuesta, Antonio Robles, José Duato	Improving Token Coherence by Multicast Coherence Messages.	PDP	2008	DBLP DOI BibTeX RDF	Token Cohence, protocol races, multicast, Cache coherence, SMP
1	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato	Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs.	HiPC	2008	DBLP DOI BibTeX RDF
1	Jun Pang, Wan Fokkink, Rutger F. H. Hofman, Ronald Veldema	Model checking a cache coherence protocol of a Java DSM implementation.	J. Log. Algebr. Program.	2007	DBLP DOI BibTeX RDF
1	Li Zhang, Chris R. Jesshope	On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
1	Ehsan Atoofian, Amirali Baniasadi	A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Liqun Cheng, John B. Carter, Donglai Dai	An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing.	HPCA	2007	DBLP DOI BibTeX RDF
1	Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai	Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	interconnect, power, SMP, cache coherence protocol
1	Colin Blundell, Joe Devietti, E. Christopher Lewis, Milo M. K. Martin	Making the fast case common and the uncommon case simple in unbounded transactional memory.	ISCA	2007	DBLP DOI BibTeX RDF	parallel programming, concurrency, transactions, transactional memory
1	Shuvendu K. Lahiri, Randal E. Bryant	Predicate abstraction with indexed predicates.	ACM Trans. Comput. Log.	2007	DBLP DOI BibTeX RDF	infinite-state verification, invariant synthesis, Formal verification, abstract interpretation, cache-coherence protocols, predicate abstraction
1	Xuemei Zhao, Karl Sammut, Fangpo He, Shaowen Qin	Split Private and Shared L2 Cache Architecture for Snooping-based CMP.	ACIS-ICIS	2007	DBLP DOI BibTeX RDF
1	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato	A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures.	HPCA	2007	DBLP DOI BibTeX RDF
1	Mrinmoy Ghosh, Hsien-Hsin S. Lee	Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems.	ICPADS	2007	DBLP DOI BibTeX RDF
1	Yi Lv, Huimin Lin, Hong Pan	Computing Invariants for Parameter Abstraction.	MEMOCODE	2007	DBLP DOI BibTeX RDF
1	Xuemei Zhao, Karl Sammut, Fangpo He	Performance Evaluation of a Novel CMP Cache Structure for Hybrid Workloads.	PDCAT	2007	DBLP DOI BibTeX RDF
1	Blas Cuesta, Antonio Robles, José Duato	An Effective Starvation Avoidance Mechanism to Enhance the Token Coherence Protocol.	PDP	2007	DBLP DOI BibTeX RDF
1	Daguang Liu, Peng Wu 0002, Huimin Lin	Symbolic Test Generation Using a Temporal Logic with Constrained Events.	Formal Methods and Hybrid Real-Time Systems	2007	DBLP DOI BibTeX RDF
1	Maurice Herlihy, Ye Sun	Distributed transactional memory for metric-space networks.	Distributed Computing	2007	DBLP DOI BibTeX RDF
1	Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya	Transition-based coverage estimation for symbolic model checking.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Min Xu, Mark D. Hill, Rastislav Bodík	A regulated transitive reduction (RTR) for longer memory race recording.	ASPLOS	2006	DBLP DOI BibTeX RDF	race recording, multithreading, determinism
1	Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, Ching-Tsun Chou	Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Pengyong Ma, Shuming Chen	MID: a Novel Coherency Protocol in Chip Multiprocessor.	CIT	2006	DBLP DOI BibTeX RDF
1	Jichuan Chang, Gurindar S. Sohi	Cooperative Caching for Chip Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
1	Noel Eisley, Li-Shiuan Peh, Li Shang	In-Network Cache Coherence.	MICRO	2006	DBLP DOI BibTeX RDF
1	Francisco J. Villa, Manuel E. Acacio, José M. García	On the Evaluation of Dense Chip-Multiprocessor Architectures.	ICSAMOS	2006	DBLP DOI BibTeX RDF
1	Artemis A. Christopoulou, Eleftherios D. Polychronopoulos	Reducing Communication Overhead and Page Faults in SDSM Platforms.	Euro-Par	2006	DBLP DOI BibTeX RDF	Software DSM Systems, Clusters, Grids, Cache Coherence Protocols, Memory Consistency Models
1	Song Fu, Cheng-Zhong Xu, Brian Wims, Ramzi Basharahil	Distributed shared arrays: A distributed virtual machine with mobility support for reconfiguration.	Cluster Computing	2006	DBLP DOI BibTeX RDF	Distributed shared arrays (DSA), Distributed virtual machine, DSA service migration, Parallel programming model
1	Hong Pan, Huimin Lin, Yi Lv	Model Checking Data Consistency for Cache Coherence Protocols.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	value-passing, symbolic transition graphs, model checking, concurrent systems, cache coherence protocols
1	Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino	Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, multiprocessor, system-on-chip, cache coherence
1	Gary Gostin, Jean-Francois Collard, Kirby Collins	The architecture of the HP Superdome shared-memory multiprocessor.	ICS	2005	DBLP DOI BibTeX RDF
1	Youtao Zhang, Lan Gao, Jun Yang 0002, Xiangyu Zhang, Rajiv Gupta	SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors.	HPCA	2005	DBLP DOI BibTeX RDF
1	Milo M. K. Martin	Formal Verification and its Impact on the Snooping versus Directory Protocol Debate.	ICCD	2005	DBLP DOI BibTeX RDF
1	Sudhindra Pandav, Konrad Slind, Ganesh Gopalakrishnan	Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification.	CHARME	2005	DBLP DOI BibTeX RDF
1	Jesse D. Bingham, Alan J. Hu	Empirically Efficient Verification for a Class of Infinite-State Systems.	TACAS	2005	DBLP DOI BibTeX RDF
1	Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin	Verifying Safety of a Token Coherence Implementation by Parametric Compositional Refinement.	VMCAI	2005	DBLP DOI BibTeX RDF
1	Maurice Herlihy, Ye Sun	Distributed Transactional Memory for Metric-Space Networks.	DISC	2005	DBLP DOI BibTeX RDF
1	M. Al-Rousan, S. Ahmed	Implementation of cache coherence protocol for COMA multiprocessor systems based on the scalable coherent interface.	Computer Standards & Interfaces	2004	DBLP DOI BibTeX RDF
1	Kylie Williams, Robert Esser	Verification of the Futurebus+ Cache Coherence protocol: A case study in model checking.	ACSC	2004	DBLP BibTeX RDF
1	Mainak Chaudhuri, Mark Heinrich	The Impact of Negative Acknowledgments in Shared Memory Scientific Applications.	IEEE Trans. Parallel Distrib. Syst.	2004	DBLP DOI BibTeX RDF	negative acknowledgment, node controller occupancy, Distributed shared memory, cache coherence protocol
1	Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar S. Sohi	Coherence decoupling: making use of incoherence.	ASPLOS	2004	DBLP DOI BibTeX RDF	coherence decoupling, coherence misses, speculative cache lookup, false sharing
1	John P. Sustersic, Ali R. Hurson	A Quality of Service (QoS) Implementation of Internet Cache Coherence.	AINA	2004	DBLP DOI BibTeX RDF
1	Weijian Fang, Cho-Li Wang, Wenzhang Zhu, Francis Chi-Moon Lau	PAT: a postmortem object access pattern analysis and visualization tool.	CCGRID	2004	DBLP DOI BibTeX RDF
1	Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu	Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood	Using Speculation to Simplify Multiprocessor Design.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra	Formal Verification of a System-on-Chip Using Computation Slicing.	ITC	2004	DBLP DOI BibTeX RDF
1	Michael Fisher, Alexei Lisitsa	Monodic ASMs and Temporal Verification.	Abstract State Machines	2004	DBLP DOI BibTeX RDF
1	Shuvendu K. Lahiri, Randal E. Bryant	Indexed Predicate Discovery for Unbounded System Verification.	CAV	2004	DBLP DOI BibTeX RDF
1	Ghassan Chehaibar	Integrating Formal Verification with Mur ? of Distributed Cache Coherence Protocols in FAME Multiprocessor System Design.	FORTE	2004	DBLP DOI BibTeX RDF