Search results for "cache design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Shobhit O. Kanaujia	Compression in cache design.	ICS	2007	DBLP DOI BibTeX RDF	cache compression, prefetching, cache design
2	Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili	An energy efficient cache design using spin torque transfer (STT) RAM.	ISLPED	2010	DBLP DOI BibTeX RDF	(STT)RAM, memory technologies, cache design
2	Miaoqing Huang, Olivier Serres, Vikram K. Narayana, Tarek A. El-Ghazawi, Gregory B. Newby	Efficient cache design for solid-state drives.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	simulation, cache design, solid-state drive
2	Jinglei Wang, Dongsheng Wang, Yibo Xue, Haixia Wang	An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
2	Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham	Cache Design for Low Power and High Yield.	ISQED	2008	DBLP DOI BibTeX RDF	reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure
2	Garo Bournoutian, Alex Orailoglu	Miss reduction in embedded processors through dynamic, power-friendly cache design.	DAC	2008	DBLP DOI BibTeX RDF	dynamic associativity, multi-core, embedded processors, data cache
2	Li Zhao, Ravi R. Iyer, Srihari Makineni, Ramesh Illikkal, Jaideep Moses, Donald Newell	Constraint-Aware Large-Scale CMP Cache Design.	HiPC	2007	DBLP DOI BibTeX RDF	Large Scale CMP, constraint-aware design, CAAM, LCMP, cache hierarchy
2	Wenlong Li, Eric Li, Aamer Jaleel, Jiulong Shan, Yurong Chen, Qigang Wang, Ravi R. Iyer, Ramesh Illikkal, Yimin Zhang, Dong Liu, Michael Liao, Wei Wei, Jinhua Du	Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	DRAM caches, small-scale CMP, medium-scale CMP, large-scale CMP, hardware-software co-simulation, terabyte-level workloads, multithreaded data mining applications, cache design, memory performance, multicore systems, memory system performance
2	Jörg Platte, Edwin Naroska, Kai Grundmann	A Cache Design for a Security Architecture for Microprocessors (SAM).	ARCS	2006	DBLP DOI BibTeX RDF
2	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
2	Lisa R. Hsu, Ravishankar R. Iyer, Srihari Makineni, Steven K. Reinhardt, Donald Newell	Exploring the cache design space for large scale CMPs.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
2	Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen	Optimizing instruction TLB energy using software and hardware techniques.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	instruction locality, translation look-aside buffer, Power consumption, compiler optimization, cache design
2	Keqiu Li, Hong Shen, Keishi Tajima	Cache Design for Transcoding Proxy Caching.	NPC	2004	DBLP DOI BibTeX RDF
2	Alexander V. Veidenbaum, Dan Nicolaescu	Low Energy, Highly-Associative Cache Design for Embedded Processors.	ICCD	2004	DBLP DOI BibTeX RDF
2	Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar	Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay.	HPCA	2002	DBLP DOI BibTeX RDF	resizable cache design, low power processor, energy aware architecture
2	Terry Lyon, Eric Delano, Cameron McNairy, Dean Mulla	Data Cache Design Considerations for the Itanium® 2 Processor.	ICCD	2002	DBLP DOI BibTeX RDF
2	Jeffrey B. Rothman, Alan Jay Smith	Sector Cache Design and Performance. (PDF / PS)	MASCOTS	2000	DBLP DOI BibTeX RDF	sector cache, simulation, architecture, workloads, multiprogramming
2	Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin	On High-Bandwidth Data Cache Design for Multi-Issue Processors.	MICRO	1997	DBLP BibTeX RDF	Locality-Based Interleaving, Multiporting, High-Bandwidth Data Supply, Multi-Bank Caches
2	Masaki Aida, Noriyuki Takahashi	Evaluation of the number of destination hosts for data networking and its application to address cache design.	ICCCN	1997	DBLP DOI BibTeX RDF	destination hosts, address cache design, address cache tables capacity, large-scale computer communication networks, packet destination addresses, cache hit probability, aging algorithm, probability, Zipf's law, data networking
2	Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau	Reducing memory latency using a small software driven array cache.	HICSS	1995	DBLP DOI BibTeX RDF	small software driven array cache, data references, array reference, nonarray reference, data cache designs, cache space, cache control mechanisms, array references, data cache performance, hardware driven data prefetching scheme, software driven cache design, array cache, low runtime overhead, performance evaluation, data structures, compiler, programming, programming, prefetching, program compilers, cache storage, cache performance, temporal locality, spatial locality, memory latency
2	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
2	William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu	The Effect of Code Expanding Optimizations on Instruction Cache Design.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	code expanding optimizations, instruction placement, function inline expansion, superscalar optimizations, small caches, medium caches, load forwarding, large caches, C compiler, code expansion, optimisation, cache memory, memory architecture, buffer storage, instruction cache, code optimization, cache design, miss ratio
2	Qing Yang	Introducing a New Cache Design into Vector Computers.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	prime-mapped cache, cache miss ratio, speed gap, memory architecture, buffer storage, cache design, performance gains, vector processor systems, Mersenne prime, cache organizations, vector computers
1	Yu-Ting Chen, Jason Cong, Hui Huang 0001, Bin Liu 0006, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman	Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design.	DATE	2012	DBLP BibTeX RDF
1	Ji Gu, Hui Guo, Patrick Li	An on-chip instruction cache design with one-bit tag for low-power embedded systems.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Ahmad Kamil Abdul Hamid, Yoshihiro Kawahara, Tohru Asami	Web Cache Design and Implementation for Efficient SNMP Monitoring towards Internet-Scale Network Management.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu	Adaptive Cache Design to Enable Reliable Low-Voltage Operation.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu	Location Cache Design and Performance Analysis for Chip Multiprocessors.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Anguo Ma, Yu Cheng, Zuocheng Xing	Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design.	J. Comput. Sci. Technol.	2011	DBLP DOI BibTeX RDF
1	Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu	Energy-efficient cache design using variable-strength error-correcting codes.	ISCA	2011	DBLP DOI BibTeX RDF
1	Shi-Wu Lo, Wen-Yan Huang, Sheng-Feng Qiu, You-Ching Lin, Kuo-Hung Lin, Homn Lin, Tei-Wei Kuo	A QoS Guaranteed Cache Design for Environment Friendly Computing.	GreenCom	2011	DBLP DOI BibTeX RDF
1	Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke	Archipelago: A polymorphic cache design for enabling robust near-threshold operation.	HPCA	2011	DBLP DOI BibTeX RDF
1	Ahmed Abousamra, Alex K. Jones, Rami G. Melhem	NoC-aware cache design for multithreaded execution on tiled chip multiprocessors.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Jishen Zhao, Cong Xu, Yuan Xie	Bandwidth-aware reconfigurable cache design with hybrid memory technologies.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Jong-Myon Kim, Sung Woo Chung, Cheol Hong Kim	Energy-aware instruction cache design using small trace cache.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Ahmed Abousamra, Rami G. Melhem, Alex K. Jones	NoC-aware cache design for chip multiprocessors.	PACT	2010	DBLP DOI BibTeX RDF
1	Jestoni V. Zarsuela, Anastacia Alvarez, Joy Alinda Reyes	A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design.	UKSim	2010	DBLP DOI BibTeX RDF
1	Fahad Ahmed, Linda Milor	Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST.	VTS	2010	DBLP DOI BibTeX RDF
1	Jun Yan, Wei Zhang 0002	Time-Predictable L2 Cache Design for High-Performance Real-Time Systems.	RTCSA	2010	DBLP DOI BibTeX RDF	unified cache, WCET analysis, real-time computing
1	Xiancheng Xu	Flow Cache Design for Improving Traffic Collection in NP-Based Network Monitor System.	ICEE	2010	DBLP DOI BibTeX RDF
1	Jin Ren, Qing Yang	A New Buffer Cache Design Exploiting Both Temporal and Content Localities.	ICDCS	2010	DBLP DOI BibTeX RDF
1	Aminul Islam, Mohd. Hasan	High Speed Cache Design Using Multi-diameter CNFET at 32nm Technology.	ICT	2010	DBLP DOI BibTeX RDF
1	Megalingam Rajesh Kannan, M. Arunkumar, V. Arjun Ashok, Krishnan Nived, C. J. Daniel	Power-Efficient Cache Design Using Dual-Edge Clocking Scheme in Sun OpenSPARC T1 and Alpha AXP Processors.	BAIP	2010	DBLP DOI BibTeX RDF
1	Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio	MODEST: a model for energy estimation under spatio-temporal variability.	ISLPED	2010	DBLP DOI BibTeX RDF	dsm scaling, spatio-temporal variability, cache design
1	Marisha Rawlins, Ann Gordon-Ross	Lightweight runtime control flow analysis for adaptive loop caching.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	embedded systems, low energy, architecture tuning, loop cache
1	Javier Lira, Carlos Molina, Antonio González	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
1	Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	A Two-Level Cache Design Space Exploration System for Embedded Applications.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	An L1 Cache Design Space Exploration System for Embedded Applications.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Guangyu Sun, Xiaoxia Wu, Yuan Xie	Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.	ISLPED	2009	DBLP DOI BibTeX RDF	thermal control, performance, 3D, L2 caches
1	Wei Chen 0009, Li Shen, Hongyi Lu, Zhiying Wang, Nong Xiao	A Light-weight Code Cache Design for Dynamic Binary Translation.	ICPADS	2009	DBLP DOI BibTeX RDF
1	Ji Gu, Hui Guo, Patrick Li	ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems.	RTCSA	2009	DBLP DOI BibTeX RDF
1	Fahad Ahmed, Linda S. Milor	Reliable cache design with detection of gate oxide breakdown using BIST.	ICCD	2009	DBLP DOI BibTeX RDF
1	Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong	Multi-execution: multicore caching for data-similar executions.	ISCA	2009	DBLP DOI BibTeX RDF	data similar execution, multicore cache design, cmp
1	Susmit Biswas, Diana Franklin, Timothy Sherwood, Frederic T. Chong	Conflict-Avoidance in Multicore Caching for Data-Similar Executions.	ISPAN	2009	DBLP DOI BibTeX RDF	Data Similar Execution, CMP, Cache Design
1	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
1	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
1	Wolfgang Puffitsch	Data caching, garbage collection, and the Java memory model.	JTRES	2009	DBLP DOI BibTeX RDF	Java memory model, garbage collection, data cache
1	Han Wan, Xiaopeng Gao, Zhiqiang Wang	Cache simulator based on GPU acceleration.	SimuTools	2009	DBLP DOI BibTeX RDF	trace-driven, multi-core, GPGPU, CUDA, cache simulator
1	Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell	Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.	HPCA	2009	DBLP DOI BibTeX RDF
1	Sangmin Seo, Jaejin Lee, Zehra Sura	Design and implementation of software-managed caches for multicores with local memory.	HPCA	2009	DBLP DOI BibTeX RDF
1	Mengxiao Liu, Weixing Ji, Xing Pu, Jiaxin Li	A Parallel Memory System Model for Multi-core Processor.	NAS	2009	DBLP DOI BibTeX RDF
1	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Jaidev K. Sridhar, Dhabaleswar K. Panda	Impact of Node Level Caching in MPI Job Launch Mechanisms.	PVM/MPI	2009	DBLP DOI BibTeX RDF
1	Jie Tao, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl	Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Simulation, Reconfigurable architecture, Multicore processor, Cache performance
1	Rung-Bin Lin	Variable-sized object packing and its applications to instruction cache design.	Computers & Electrical Engineering	2008	DBLP DOI BibTeX RDF
1	Mohammed Abid Hussain, Madhu Mutyam	Block remap with turnoff: A variation-tolerant cache design technique.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Chuanjun Zhang, Bing Xue	Two dimensional highly associative level-two cache design.	ICCD	2008	DBLP DOI BibTeX RDF
1	Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue	Improved Policies for Drowsy Caches in Embedded Processors.	DELTA	2008	DBLP DOI BibTeX RDF	Low Power Cache Design, Leakage Energy, Drowsy Cache
1	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Architecting Efficient Interconnects for Large Caches with CACTI 6.0.	IEEE Micro	2008	DBLP DOI BibTeX RDF	CACTI 6.0, on-chip interconnects, cache design
1	Yen-Jen Chang	Exploiting frequent opcode locality for power efficient instruction cache.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	frequent opcode locality, instruction cache, power-efficient
1	Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abdulaziz Eker	Characterizing and modeling the behavior of context switch misses.	PACT	2008	DBLP DOI BibTeX RDF	context switch misses, stack distance profiling, prefetching, analytical model
1	Mahmoud Ben Naser, Csaba Andras Moritz	Power and performance tradeoffs with process variation resilient adaptive cache architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	process variations, leakage power, adaptive cache
1	Arifa Nisar, Wei-keng Liao, Alok N. Choudhary	Scaling parallel I/O performance through I/O delegate and caching system.	SC	2008	DBLP DOI BibTeX RDF
1	Chuanjun Zhang	Reducing cache misses through programmable decoders.	TACO	2008	DBLP DOI BibTeX RDF	low power, Cache, dynamic optimization
1	Aviral Shrivastava, Ilya Issenin, Nikil Dutt	A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Jason Zebchuk, Srihari Makineni, Donald Newell	Re-examining cache replacement policies.	ICCD	2008	DBLP DOI BibTeX RDF
1	Wenlong Huang, Taoying Liu, Yi Zhao	Query Evaluation and Performance Optimization in Distributed Community Data Sharing System Based on Web Services.	IEEE SCC	2008	DBLP DOI BibTeX RDF	web services, distributed system, community, data sharing
1	Chih-Wen Hsueh, Jen-Feng Chung, Lan-Da Van, Chin-Teng Lin	Anticipatory access pipeline design for phased cache.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Mahmoud A. Bennaser, Yao Guo, Csaba Andras Moritz	Data Memory Subsystem Resilient to Process Variations.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Nikola Vujic, Marc González, Xavier Martorell, Eduard Ayguadé	Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture.	LCPC	2008	DBLP DOI BibTeX RDF	Cell BE Architecture, Modulo Scheduling, Pre-fetching, Software Cache
1	Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka	4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Ahmad Zmily, Christos Kozyrakis	A low power front-end for embedded processors using a block-aware instruction set.	CASES	2007	DBLP DOI BibTeX RDF	instruction re-ordering, low power front-end, software hints, tagless instruction cache, unified instruction cache and BTB, instruction prefetching
1	Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau	A predictive decode filter cache for reducing power consumption in embedded processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Cache, embedded processors, power optimization
1	Hyunjin Lee, Sangyeun Cho, Bruce R. Childers	Exploring the interplay of yield, area, and performance in processor caches.	ICCD	2007	DBLP DOI BibTeX RDF
1	Ja Chun Ku, Yehea I. Ismail	Attaining Thermal Integrity in Nanometer Chips.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz	Designing Memory Subsystems Resilient to Process Variations.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Mohsen Soryani, Mohsen Sharifi, Mohammad Hossein Rezvani	Performance Evaluation of Cache Memory Organizations in Embedded Systems.	ITNG	2007	DBLP DOI BibTeX RDF
1	Jason Zebchuk, Elham Safi, Andreas Moshovos	A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.	MICRO	2007	DBLP DOI BibTeX RDF
1	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Nahalal: Cache Organization for Chip Multiprocessors.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	Jason Zebchuk, Andreas Moshovos	A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	Wei Pei, Wen-Ben Jone, Yiming Hu	Fault Modeling and Detection for Drowsy SRAM Caches.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares	Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.	HiPEAC	2007	DBLP DOI BibTeX RDF
1	Hyemee Park, Moonseong Kim, Hyunseung Choo	Intra Routing Protocol with Hierarchical and Distributed Caching in Nested Mobile Networks.	ICESS	2007	DBLP DOI BibTeX RDF
1	Alberto Ros, Manuel E. Acacio, José M. García	An efficient cache design for scalable glueless shared-memory multiprocessors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	L2, directory structure, glueless shared-memory multiprocessors, cache, cache coherence, memory wall
1	Jay Nelson	Concurrent caching.	Erlang Workshop	2006	DBLP DOI BibTeX RDF	concurrent cache, erlang
1	Tony Givargis	Zero cost indexing for improved processor cache performance.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	index hashing, Cache optimization, design exploration
1	Derek Bruening, Vladimir Kiriansky, Timothy Garnett, Sanjeev Banerji	Thread-Shared Software Code Caches.	CGO	2006	DBLP DOI BibTeX RDF
1	Chuanjun Zhang	Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches.	ISCA	2006	DBLP DOI BibTeX RDF