Search results for "cache miss penalty"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Yingjie Zhao, Nong Xiao	Saber: Sequential Access Based cachE Replacement to Reduce the Cache Miss Penalty.	ICYCS	2008	DBLP DOI BibTeX RDF
2	Sanghyun Park, Aviral Shrivastava, Yunheung Paek	Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors.	DATE	2008	DBLP DOI BibTeX RDF
2	Yingjie Zhao, Nong Xiao	Bargain Cache: Using File-System Metadata to Reduce the Cache Miss Penalty.	PDCAT	2008	DBLP DOI BibTeX RDF
2	Mark J. Clement, Michael J. Quinn	Multivariate statistical techniques for parallel performance prediction.	HICSS	1995	DBLP DOI BibTeX RDF	multivariate statistical techniques, parallel performance prediction, multicomputer efficiency, program execution time, architectural characterization, algorithmic characterization, critical model parameters, cache miss penalty, predicted execution time, standard error values, large variance values, performance evaluation, parallel processing, performance model, statistical analysis, data analysis, software performance evaluation, variance, confidence interval, random variables, message latency, multivariate data analysis, model parameters
1	Arno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen	Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip.	DATE	2008	DBLP DOI BibTeX RDF
1	Alexandru Andrei, Petru Eles, Zebo Peng, Jakob Rosen	Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Jakob Rosen, Alexandru Andrei, Petru Eles, Zebo Peng	Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.	RTSS	2007	DBLP DOI BibTeX RDF
1	Moon-Hee Choi, Woo-Chan Park, Francis Neelamkavil, Tack-Don Han, Shin-Dug Kim	An Effective Visibility Culling Method Based on Cache Block.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	visible/surface algorithms, Computer graphics, cache memories, graphics processors
1	Kuang-Hui Chi, Ji-Han Jiang, Li-Hsing Yen	Cost-Effective Caching for Mobility Support in IEEE 802.1X Frameworks.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	independent reference model, Robust Security Network, cache, Wireless Local Area Network, fast handoff
1	Xiaoqin Ma, Gene Cooperman	Fast Query Processing by Distributing an Index over CPU Caches.	CLUSTER	2005	DBLP DOI BibTeX RDF
1	Kenneth W. Batcher, Robert A. Walker	Cluster miss prediction for instruction caches in embedded networking applications.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	compulsory cache misses, hiding memory latency, embedded systems, networking, WCET, cache design, cache prefetch
1	Zhao Zhang, Zhichun Zhu, Xiaodong Zhang	Design and Optimization of Large Size and Low Overhead Off-Chip Caches.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau	Power Savings in Embedded Processors through Decode Filer Cache.	DATE	2002	DBLP DOI BibTeX RDF
1	Yen-Kuang Chen, Eric Debes, Rainer Lienhart, Matthew J. Holliman, Minerva M. Yeung	Evaluating and Improving Performance of Multimedia Applications on Simultaneous Multi-Threading.	ICPADS	2002	DBLP DOI BibTeX RDF
1	Yen-Kuang Chen, Rainer Lienhart, Eric Debes, Matthew J. Holliman, Minerva M. Yeung	The Impact of SMT/SMP Designs on Multimedia Software Engineering - A Workload Analysis Study.	ISMSE	2002	DBLP DOI BibTeX RDF
1	Joan-Manuel Parcerisa, Antonio González	Improving Latency Tolerance of Multithreading through Decoupling.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Access/execute decoupling, instruction-level parallelism, simultaneous multithreading, latency hiding, hardware complexity
1	Sung-Kwan Kim, Sang Lyul Min, Rhan Ha	Analysis of the Impacts of Overestimation Sources on the Accuracy of Worst Case Timing Analysis. (PDF / PS)	IEEE Real-Time Systems Symposium	1999	DBLP DOI BibTeX RDF	real-time systems, WCET analysis
1	Hiroaki Fujii, Yoshiko Yasuda, Hideya Akashi, Yasuhiro Inagami, Makoto Koga, Osamu Ishihara, Masamori Kashiyama, Hideo Wada, Tsutomu Sumimoto	Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF