Search results for "cache storage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Anirudh Badam, KyoungSoo Park, Vivek S. Pai, Larry L. Peterson	HashCache: Cache Storage for the Next Billion.	NSDI	2009	DBLP BibTeX RDF
1	Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong	Multi-execution: multicore caching for data-similar executions.	ISCA	2009	DBLP DOI BibTeX RDF	data similar execution, multicore cache design, cmp
1	Andrew DeOrio, Ilya Wagner, Valeria Bertacco	Dacota: Post-silicon validation of the memory subsystem in multi-core designs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Kyle J. Nesbit, James Laudon, James E. Smith	Virtual private caches.	ISCA	2007	DBLP DOI BibTeX RDF	quality of service, chip multiprocessor, soft real-time, shared caches, performance isolation
1	Xiaodan Wang, Tanu Malik, Randal C. Burns, Stratos Papadomanolakis, Anastassia Ailamaki	A Workload-Driven Unit of Cache Replacement for Mid-Tier Database Caching.	DASFAA	2007	DBLP DOI BibTeX RDF
1	Xiaofeng Gao, Allan Snavely, Larry Carter	Path Grammar Guided Trace Compression and Trace Approximation.	HPDC	2006	DBLP DOI BibTeX RDF	path grammar guided trace compression, trace approximation, PGGTC, Sequitur algorithm, selective dumping, memory signature, parallel computer, computer architecture, parallel machine, trace-driven simulation, cache storage
1	Jay Nelson	Concurrent caching.	Erlang Workshop	2006	DBLP DOI BibTeX RDF	concurrent cache, erlang
1	Bo Yang, Ali R. Hurson, Yu Jiao	On the Content Predictability of Cooperative Image Caching in Ad Hoc Networks.	MDM	2006	DBLP DOI BibTeX RDF
1	Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh	Adaptive Caches: Effective Shaping of Cache Behavior to Workloads.	MICRO	2006	DBLP DOI BibTeX RDF
1	Michael Zhang, Krste Asanovic	Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
1	Weining Qian, Linhao Xu, Shuigeng Zhou, Aoying Zhou	CoCache: Query Processing Based on Collaborative Caching in P2P Systems.	DASFAA	2005	DBLP DOI BibTeX RDF
1	Xiu Wu, Kian-Lee Tan	A Hash-Based Collaborative Transcoding Proxy System.	APWeb	2003	DBLP DOI BibTeX RDF
1	Emmanuel Cecchet	Whoops! : A Clustered Web Cache for DSM Systems using Memory Mapped Networks.	ICDCS Workshops	2002	DBLP DOI BibTeX RDF	memory mapped network, TCP handoff, on the fly compression, cluster, web cache, DSM, SCI
1	Xubin He, Qing Yang, Ming Zhang	Introducing SCSI-to-IP Cache for Storage Area Networks. (PDF / PS)	ICPP	2002	DBLP DOI BibTeX RDF
1	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	A reconfigurable multifunction computing cache architecture.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Clare Churcher, Alan McKinnon, Roger Jarquin	Visualising the influence of data structure choice on the performance of a distributed database system.	APSEC	2000	DBLP DOI BibTeX RDF	data structure choice, object oriented distributed database system performance, cache monitoring software, textual description, data structures, distributed databases, project management, object-oriented databases, visualisation, data visualisation, client-server systems, software development management, cache storage, system monitoring, software project
1	Michael A. Bender, Erik D. Demaine, Martin Farach-Colton	Cache-Oblivious B-Trees.	FOCS	2000	DBLP DOI BibTeX RDF	cache-oblivious B-trees, dynamic search-tree data structures, optimal search bound, amortized memory transfers, computational complexity, memory hierarchy, cache storage, tree data structures, insertions, deletions, tree searching, hierarchical memory, worst-case bounds
1	Sudipto Guha, Adam Meyerson, Kamesh Munagala	Hierarchical Placement and Network Design Problems.	FOCS	2000	DBLP DOI BibTeX RDF	subscriber loops, hierarchical placement, layered network design problems, constant approximations, bounded miss rates, minimum total cost, routing demand, layered caching scenarios, combinatorial approximation, multi-level facility location problem, load-balanced facility location problem, open facilities, access network design problem, resource allocation, facility location, cache storage, file organisation, approximation theory, hierarchical systems, network synthesis, hierarchical caching
1	Simon Baatz, Wolfgang Hansmann, Jens Tölle	Security of Routing Cache Updates in Cellular IP. (PDF / PS)	LCN	2000	DBLP DOI BibTeX RDF	routing cache updates security, micro mobility solution, geographical area, IP datagrams, fast handoff control, wide area mobility, location information protection, mobile devices, transport protocols, mobile IP, telecommunication network routing, cache storage, data communication, telecommunication security, packet radio networks, cellular radio, mobile stations, cellular IP
1	T. T. Tay, Y. Feng, M. N. Wijeysundera	A Distributed Internet Caching System. (PDF / PS)	LCN	2000	DBLP DOI BibTeX RDF	distributed Internet caching system, distributed Web caching system, cache server, storage protocol, Internet, reliability, computer network, distributed memory systems, cache storage, access protocols, access protocol, data consistency, network servers, storage capacity, memory protocols
1	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	A reconfigurable multi-function computing cache architecture.	FPGA	2000	DBLP DOI BibTeX RDF
1	Stephen Wagner, Zahir Tari	A Caching Protocol to Improve CORBA Performance.	Australasian Database Conference	2000	DBLP DOI BibTeX RDF
1	Zahir Tari, Slimane Hammoudi, Stephen Wagner	A COBRA Object-Based Caching with Consistency.	DEXA	1999	DBLP BibTeX RDF
1	Edith Cohen, Balachander Krishnamurthy, Jennifer Rexford	Evaluating Server-Assisted Cache Replacement in the Web.	ESA	1998	DBLP DOI BibTeX RDF
1	Nigel P. Topham, Antonio González, José González	The Design and Performance of a Conflict-Avoiding Cache.	MICRO	1997	DBLP BibTeX RDF	cache architecture design, conflict miss ratios, conflict-avoiding cache performance, data access cost minimization, high performance architectures, multi-level memory hierarchies, polynomial modulus functions, cache storage, main memory
1	Thomas Stricker, Thomas R. Gross	Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems.	HPCA	1997	DBLP DOI BibTeX RDF	nonuniform bandwidth, memory system performance characterization, local memory accesses, remote write, cost benefit model, DEC Alpha based parallel systems, DEC-Alpha processor architecture, DEC 8400, scalability, compiler, parallel systems, empirical evaluation, memory architecture, coherency, cache storage, access pattern, spatial locality, local memory, global address space, Cray T3E, Cray T3D, clock speed
1	Kuang-Chih Liu, Chung-Ta King	On the effectiveness of sectored caches in reducing false sharing misses. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF	sectored caches, false sharing misses, bus-based multiprocessors, coherence unit, MESI protocol, LU, SORBYR, SORBYC, benchmarks, FFT, performance metric, cache storage, Radix
1	John Heinlein, Kourosh Gharachorloo, Robert P. Bosch Jr., Mendel Rosenblum, Anoop Gupta	Coherent Block Data Transfer in the FLASH Multiprocessor. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	FLASH multiprocessor, block data transfer, multiple communication protocols, embedded protocol processor, protocol, shared memory, prefetching, cache storage, FLASH, cache coherence protocol, multiprocessor architecture, MAGIC
1	Rong-Yuh Hwang	An Efficient Technique of Instruction Scheduling on a Superscalar-Based Mulprocessor. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	FLASH multiprocessor, block data transfer, multiple communication protocols, embedded protocol processor, protocol, shared memory, prefetching, cache storage, FLASH, cache coherence protocol, multiprocessor architecture, MAGIC
1	Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia	A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures.	MICRO	1996	DBLP BibTeX RDF	LRU replacement, disk caching scheme, dynamic rescheduling, first-time page faults, high-overhead programs, low overhead object code compatibility, overhead-based replacement, page replacement policies, persistent rescheduled-page cache, run-time software rescheduling, simulations, cache storage, VLIW architectures, program executions, operating system support, program performance
1	Tien-Fu Chen	Efficient trace-sampling simulation techniques for cache performance analysis.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	efficient trace sampling simulation techniques, cache performance analysis, large cache simulation, space sampling technique, index of locality, trace references, time sampling approach, inter loop intervals, time sampling technique, representative performance results, loop execution, simulation time, small estimate errors, performance evaluation, virtual machines, digital simulation, performance metric, cache storage, stratified sampling, loop iterations, trace reduction
1	Pablo Ibáñez, Víctor Viñals	Performance Assessment of Contents Management in Multilevel On-Chip Caches.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multilevel on-chip caches, Inclusion contents management, Exclusion, second-level cache miss ratio, system CPI, floating point SPEC'92 benchmarks, performance metrics, contents management, cache storage, design space, performance assessment, Demand
1	Anders Landin, Fredrik Dahlgren	Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	bus-based COMA, standard UMA architecture, program-driven simulation, SPLASH, cache only memory architecture, shared-memory multiprocessors, shared memory systems, memory architecture, cache storage, shared-bus multiprocessors
1	Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh	The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention
1	Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura	An Optical Bus Computer Cluster with a deferred cache coherence protocol. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	Optical Bus Computer Cluster, deferred cache coherence protocol, optical star-coupler, one-hop simultaneous broadcasting, wavelength multiplexing, deferred cache coherence, coherence maintenance, protocols, wavelength-division multiplexing, optical interconnections, cache storage
1	Edward David Moreno Ordonez, Sergio Takeo Kofuji	Performance evaluation of the fixed sequential prefetching on a bus-based multiprocessor: preliminary results.	ISPAN	1996	DBLP DOI BibTeX RDF	fixed sequential prefetching, bus-based multiprocessor, sequential prefetching, OBL policy, performance evaluation, performance evaluation, Petri nets, Petri nets, shared memory systems, shared memory systems, cache storage, data prefetching
1	Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King	Performance of Shared Cache on Multithreaded Architectures.	PDP	1996	DBLP DOI BibTeX RDF	shared cache performance, trace-driven simulation technique, storage hierarchy system, multithreaded execution environment, multithread scheduling techniques, server/workstation workload mix, MRU priority scheduling scheme, round-robin scheduling method, absolute hit ratio, concurrent threads, simulation, performance evaluation, parallel architectures, shared memory systems, processor scheduling, cache storage, multithreaded architectures, program traces, set associativity, cache size, direct-map cache
1	Sung-Kwan Kim, Sang Lyul Min, Rhan Ha	Efficient worst case timing analysis of data caching. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block
1	Chang-Gun Lee, Joosun Hahn, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim	Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. (PDF / PS)	IEEE Real-Time Systems Symposium	1996	DBLP DOI BibTeX RDF	cache-related preemption delay, unpredictable variation, task execution time, per-task analysis, preemption cost, execution point, linear programming technique, experimental results, cache storage, worst case response time, fixed-priority preemptive scheduling
1	Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe	Cache modeling for real-time software: beyond direct mapped instruction caches. (PDF / PS)	IEEE Real-Time Systems Symposium	1996	DBLP DOI BibTeX RDF	direct mapped instruction caches, worst case timing analysis, cache hits, set associative instruction caches, unified caches, cinderella, research, integer-linear-programming, worst case execution time, data caches, cache storage, design tool, memory performance, cache misses, real-time software, tight bound, cache modeling, hardware system
1	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
1	Ricardo Bianchini, Leonidas I. Kontothanassis	Algorithms for categorizing multiprocessor communication under invalidate and update-based coherence protocols.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	shared-memory multiprocessor communication, invalidate-based cache coherence protocols, update-based cache coherence protocols, reference patterns, sharing patterns, useless data traffic, data traffic categorization, parallel programming, parallel programs, virtual machines, transaction processing, shared memory systems, coherence, cache storage, telecommunication traffic, cache misses, simulation algorithms, update transactions, memory protocols
1	Frank Mueller, David B. Whalley	Fast instruction cache analysis via static cache simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	instruction cache analysis, static cache simulation, cache configuration, instruction reference, cache hit, counter incrementation, code execution frequency, local state information updating, frequency counters, program exit, virtual machines, cache storage, program diagnostics, dynamic simulation, cache miss
1	Rakesh D. Barve, Edward F. Grove, Jeffrey Scott Vitter	Application-Controlled Paging for a Shared Cache (Extended Abstract).	FOCS	1995	DBLP DOI BibTeX RDF	application-controlled paging, application processes, worst-case interleaving, global paging performance, shared memory systems, cache storage, shared cache, page fault, paged storage
1	Eric Torng	A Unified Analysis of Paging and Caching.	FOCS	1995	DBLP DOI BibTeX RDF	unified analysis, two-level memory hierarchy, miss penalty, caching, paging, cache storage, paged storage
1	Mårten Björkman, Fredrik Dahlgren, Per Stenström	Using hints to reduce the read miss penalty for flat COMA protocols.	HICSS	1995	DBLP DOI BibTeX RDF	read miss penalty, flat COMA protocols, flat cache-only memory architectures, attraction-memory miss, directory interrogation, network traversals, data copy holder identity tracking, benchmark applications, protocol complexity, performance evaluation, transaction processing, memory architecture, cache storage, performance improvement, hints, architectural simulations, memory protocols
1	Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu	A study of the effects of compiler-controlled speculation on instruction and data caches.	HICSS	1995	DBLP DOI BibTeX RDF	compiler-controlled speculation, nonnumeric programs, speculatively scheduled code, aggressive speculation models, scheduling, performance evaluation, parallel programming, time, instruction level parallelism, program compilers, data caches, cache storage, instruction cache, cache misses, performance results
1	Uwe Busbach	Distributed work management: an application area for mobile computing.	HICSS	1995	DBLP DOI BibTeX RDF	distributed work management, asynchronous CSCW applications, mobile equipment, activity coordination, distributed work environments, task manager implementation, mobile task manager, user driven data caching, mobile computing, computer supported cooperative work, groupware, distributed processing, software, hardware, wide area networks, wide area networks, mobile technology, cache storage, portable computers, data objects
1	Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau	Reducing memory latency using a small software driven array cache.	HICSS	1995	DBLP DOI BibTeX RDF	small software driven array cache, data references, array reference, nonarray reference, data cache designs, cache space, cache control mechanisms, array references, data cache performance, hardware driven data prefetching scheme, software driven cache design, array cache, low runtime overhead, performance evaluation, data structures, compiler, programming, programming, prefetching, program compilers, cache storage, cache performance, temporal locality, spatial locality, memory latency
1	John G. Cleary, Murray Pearson, Husam Kinawi	The architecture of an optimistic CPU: the WarpEngine.	HICSS	1995	DBLP DOI BibTeX RDF	optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory
1	Sreeram Duvvuru, Siamak Arya	Evaluation of a branch target address cache.	HICSS	1995	DBLP DOI BibTeX RDF	branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes
1	Alexandre E. Eichenberger, Santosh G. Abraham	Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors.	HICSS	1995	DBLP DOI BibTeX RDF	fuzzy barriers, overall execution time, parallel region, nondeterministic load imbalance modelling, random replacement policy, processor caches, cyclic access stream, interprocessor synchronization, 64-processor KSR system, Kendall Square Research system, random first-level caches, performance evaluation, resource allocation, concurrency control, synchronisation, shared memory systems, cache storage, variance, performance improvement, network contention, hit ratio, scalable shared-memory multiprocessors
1	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
1	Wesley K. Kaplow, William Maniatty, Boleslaw K. Szymanski	Impact of memory hierarchy on program partitioning and scheduling.	HICSS	1995	DBLP DOI BibTeX RDF	parallel program scheduling, nonlinear cache-miss rates, loop nest execution simulation, architecturally parameterized cache simulator, loop range, cache-miss ratio, loop interchange, iteration-space blocking, program runtime estimation, IBM 9076 SP1, SuperSPARC, scheduling, parallel programming, optimisation, memory hierarchy, processor scheduling, software performance evaluation, memory architecture, cache storage, program optimization, cache performance, program control structures, program partitioning, Intel i860
1	Zhiyong Li 0002, Peter Mills, John H. Reif	Models and resource metrics for parallel and distributed computation.	HICSS	1995	DBLP DOI BibTeX RDF	resource metrics, architectural details, generic parameters, network communication costs, LogP-HMM model, parameterized network model, sequential hierarchical memory model, multilevel memory, local cache, near-optimal sorting, parallel processing, parallel computation, distributed algorithms, distributed computation, resource allocation, sorting, fast Fourier transforms, parallel machines, memory hierarchy, cache storage, design principles, asynchrony, parallel models, input/output, synchronous models, fast Fourier transform algorithms
1	Stephen Lucci, Izidor Gertner, Anil Gupta, Uday Hegde	Reflective-memory multiprocessor.	HICSS	1995	DBLP DOI BibTeX RDF	reflective-memory multiprocessor, hardware-supported data replication, multiple computers, memory semantics, reflective memory implementation, Encore Infinity, spinlocks, cache coherency problems, massive replication, recovery procedure, crashed nodes, reliability, fault tolerant computing, shared memory systems, distributed memory systems, system recovery, cache storage, cached architectures, distributed shared memory multiprocessor
1	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
1	Igor Tartalja, Veljko M. Milutinovic	A survey of software solutions for maintenance of cache consistency in shared memory multiprocessors.	HICSS	1995	DBLP DOI BibTeX RDF	cache consistency maintenance, abstract multidimensional criterion-space, potentially useful solutions, classification, data integrity, concurrency control, survey, shared memory systems, reviews, cache storage, shared-memory multiprocessor systems, software solutions
1	Jai Menon	A Performance Comparison of RAID-5 and Log-Structured Arrays. (PDF / PS)	HPDC	1995	DBLP DOI BibTeX RDF	RAID-5, log-structured arrays, transaction-processing workloads, outboard disk controller, nonvolatile cache, physical disks, storage management, cache storage, performance comparison, compression ratio
1	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
1	Chi-Hung Chi, Siu-Chung Lau	Reducing data access penalty using intelligent opcode-driven cache prefetching. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	data access penalty, intelligent opcode-driven, LOAD-UPDATE, LOAD-MODIFY, IBM PowerPC, HP Precision Architecture, intelligent data prefetching, instruction decode unit, storage management, data cache, cache storage, cache prefetching
1	Eddy de Greef, Francky Catthoor, Hugo De Man	Memory organization for video algorithms on programmable signal processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	video algorithms, programmable signal processors, memory-intensive algorithms, compile-time data caching, motion estimation type algorithms, performance, image processing, video, mapping, DSP, imaging, storage management, memory architecture, cache storage, digital signal processing chips, buffer sizes
1	Martin C. Herbordt, Charles C. Weems	An empirical study of datapath, memory hierarchy, and network in SIMD array architectures. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	SIMD array architectures, SIMD arrays, ENPASSANT, router network, local transfers, performance evaluation, performance, parallel architectures, broadcast, virtual machines, memory hierarchy, reduction, associativity, memory architecture, cache storage, simulation environment, datapath, block size
1	Murali Kadiyala, Laxmi N. Bhuyan	A dynamic cache sub-block design to reduce false sharing. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	dynamic cache sub-block design, bus traffic, dynamic sub-block coherence protocol, simulation results, memory architecture, cache storage, false sharing, memory protocols
1	Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore	The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
1	Farnaz Mounes-Toussi, David J. Lilja	Write buffer design for cache-coherent shared-memory multiprocessors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	write-buffer configurations, one word per buffer entry, one block per buffer entry, write-through, write-back, competitive-performance, shared-memory multiprocessors, shared memory systems, cache-coherent, memory architecture, buffer storage, cache storage, execution-driven simulator, write policies
1	Stephen J. Walsh, John A. Board	Pollution control caching. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	pollution control caching, high speed processors, bandwidth mismatch, standard DRAMS, on-chip caches, miss ratio statistics, expected clock cycles per instruction, main memory latencies, PCC+VB, discrete event simulation, memory architecture, trace driven simulation, cache storage, memory performance, ANOVA, DRAM chips
1	Robert Yung, Neil C. Wilhelm	Caching processor general registers. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file
1	Gyungho Lee	An assessment of COMA multiprocessors. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate
1	Tong-Yee Lee, C. S. Raghavendra, John B. Nicholas	Parallel implementation of ray-tracing algorithm on the Intel Delta parallel computer. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	ray-tracing algorithm, Intel Delta parallel computer, computer graphics techniques, high quality image rendering, memory storage, database distribution, distributed subimages, previous workload requests, parallel algorithms, load balancing, resource allocation, ray tracing, parallel machines, processor, cache storage, parallel implementation, rendering (computer graphics), CPU time, complex scenes
1	Qiang Li, David B. Gustavson	Fat-tree for local area multiprocessors. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	local area multiprocessors, LAMP, high-performance low-cost parallel computing, LAN-size area, remote data cache, high performance multiprocessor, point-to-point physical connections, high system throughput, fat-tree topology, cable length, link clock speeds, biCMOS chips, performance evaluation, parallel architectures, parallel architecture, multiprocessor interconnection networks, local area networks, latency, packet switching, packet switch, CMOS, shared memory systems, distributed memory systems, simulation results, cache storage, system buses, SCI, buffer requirements, distributed-shared-memory multiprocessor, scalable coherent interface
1	Michael Marchetti, Leonidas I. Kontothanassis, Ricardo Bianchini, Michael L. Scott	Using simple page placement policies to reduce the cost of cache fills in coherent shared-memory systems. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	page placement policies, cache fills, OS-based page placement, page replication, performance, shared memory systems, shared-memory systems, storage management, operating systems (computers), cache storage, paged storage, distributed shared memory multiprocessors, page migration
1	Qidong Xu, Patricia J. Teller	Unified vs. split TLBs and caches in shared-memory MP systems. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	data references, performance evaluation, caches, discrete event simulation, shared-memory multiprocessors, shared memory systems, trace-driven simulations, cache storage, performance gains, translation-lookaside buffer
1	José V. Busquets-Mataix, Juan José Serrano	The impact of extrinsic cache performance on predictability of real-time systems.	RTCSA	1995	DBLP DOI BibTeX RDF	tighter bounds, cached programs, extrinsic cache behavior, inter-task cache interference, cache predictability, performance evaluation, real-time systems, real-time systems, predictability, worst case execution time, schedulability analysis, cache storage, cache performance
1	O. Hammami	Real time aspects of cluster based caches.	RTCSA	1995	DBLP DOI BibTeX RDF	cluster based caches, performance evaluation, performance, real-time systems, predictability, cache storage, hit ratio, cache organization, hit time
1	Dominique Thiébaut, Harold S. Stone	Improving Disk Cache Hit-Ratios Through Cache Partitioning.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	fully associative cache memories, buffer storage, adaptive algorithm, cache storage, content-addressable storage, cache partitioning, magnetic disc storage, hit-ratios, disk cache, queuing network model
1	Helmut Weberpals	Improving the Vector Performance via Algorithmic Domain Decomposition.	CONPAR	1990	DBLP DOI BibTeX RDF