Search results for "cadence"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Jayanta Mukherjee, Jason Parry, WenHua Dai, Patrick Roblin, Steven B. Bibyk, Jongsoo Lee	RFIC Loadpull Simulations Implementing Best Practice RF and Mixed-Signal Design using an Integrated Agilent and Cadence EDA tool.	MSE	2003	DBLP DOI BibTeX RDF
2	Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg D. Croft, Adelmo Ortiz-Conde	Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Chiraz BenAbdelkader, Larry S. Davis, Ross Cutler	Stride and Cadence as a Biometric in Automatic Person Identification and Verification. (PDF / PS)	FGR	2002	DBLP DOI BibTeX RDF
2	Marta Z. Kwiatkowska, Gethin Norman, Roberto Segala	Automated Verification of a Randomized Distributed Consensus Protocol Using Cadence SMV and PRISM.	CAV	2001	DBLP DOI BibTeX RDF
2	Toby Schaffer, Andy Stanaski, Alan Glaser, Paul D. Franzon	The NCSU Cadence Design Kit for IC Fabrication through MOSIS.	MSE	1999	DBLP DOI BibTeX RDF
2	Gerard A. Allan, Anthony J. Walton	Efficient critical area estimation for arbitrary defect shapes. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	critical area estimation, arbitrary defect shapes, circular defects, elliptical defects, rod shaped defects, arbitrary shaped defects, Edinburgh Yield Estimator, Cadence layout editor, EYE-sampling tool, EYE, EYES, integrated circuit yield, IC layout
2	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
2	S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri	A VLSI chip for image compression using variable block size segmentation. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	variable block size segmentation, VBSS scheme, variable size blocks, redundancy features, maximum compression, nearest neighbor communication, CMOS VLSI chip, image characteristics extraction subsystem, Cadence design tools, VLSI, parallelism, pipelining, image compression, VLSI architecture, VLSI implementation, lossless image compression, VLSI chip, coding techniques
2	Vamsi Krishna, Abdel Ejnioui, N. Ranganathan	A tree matching chip.	VLSI Design	1996	DBLP DOI BibTeX RDF	tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture
1	Alex J. Cannon	Neural networks for probabilistic environmental prediction: Conditional Density Estimation Network Creation and Evaluation (CaDENCE) in R.	Computers & Geosciences	2012	DBLP DOI BibTeX RDF
1	Lijuan Luo, Tan Yan, Qiang Ma 0002, Martin D. F. Wong, Toshiyuki Shibuya	B-escape: a simultaneous escape routing algorithm based on boundary routing.	ISPD	2010	DBLP DOI BibTeX RDF	PCB routing, dense circuit boards, computer-aided design, escape routing
1	Joseph Diggins	Detecting Cross-Fades in Interlaced Video With 3: 2 Film Cadence.	IEEE Trans. Circuits Syst. Video Techn.	2009	DBLP DOI BibTeX RDF
1	Hyung-Ook Park, Alireza A. Dibazar, Theodore W. Berger	Cadence analysis of temporal gait patterns for seismic discrimination between human and quadruped footsteps.	ICASSP	2009	DBLP DOI BibTeX RDF
1	M. Suresh, Kiran Sadangi, Santoshi Sahu, A. K. Panda	A Novel Flash Analog-to-Digital Converter Design Using Cadence Tool.	ARTCom	2009	DBLP DOI BibTeX RDF
1	Soheil Modirzadeh, Brian Fuller, Sandeep Mirchandani, Jon McDonald, Ran Avinun, Camille Kokozaki	It is all about power analysis, exploration and trade-offs.	ISLPED	2009	DBLP DOI BibTeX RDF	IDT, NXP, broadcom, cadence, system design and verification, technical panel, low power, low power design
1	Yang Liu, Ashok Kumar Srivastava, Yao Xu	A switchable PLL frequency synthesizer and hot carrier effects.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos phase-locked loop, hot carrier effects, jitter, voltage-controlled oscillator, phase noise
1	Rajdeep Mukhopadhyay, S. K. Panda, Pallab Dasgupta, John Gough	Instrumenting AMS assertion verification on commercial platforms.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion
1	Fahmi Elsayed, Mohamed F. Ibrahim, Yehya H. Ghallab, Wael M. Badawy, Brent Maundy	A new 90NM CMOS current feedback operational amplifier.	CCECE	2009	DBLP DOI BibTeX RDF
1	Yngvar Berg, Omid Mirmotahari	Ultra low-voltage switched current mirror.	DDECS	2009	DBLP DOI BibTeX RDF
1	Yngvar Berg, Omid Mirmotahari	Low voltage precharge CMOS logic.	DDECS	2009	DBLP DOI BibTeX RDF
1	Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko	Experience in Virtual Testing of RSD cyclic A/D converters.	DDECS	2009	DBLP DOI BibTeX RDF
1	Maruthi Chandrasekhar Bh, Sudeb Dasgupta	A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications.	ISQED	2009	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas	Design of a Low Power, Variable-Resolution Flash ADC.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Rasmus R. Jensen, Rasmus R. Paulsen, Rasmus Larsen	Analysis of Gait Using a Treadmill and a Time-of-Flight Camera.	Dyn3D	2009	DBLP DOI BibTeX RDF	computer vision, Markov random fields, motion capture, gait analysis, Time-of-flight camera
1	Luís Mendes, Eduardo José Solteiro Pires, Paulo B. de Moura Oliveira, José António Tenreiro Machado, Nuno M. Fonseca Ferreira, João Caldinhas Vaz, Maria J. Rosário	Design Optimization of Radio Frequency Discrete Tuning Varactors.	EvoWorkshops	2009	DBLP DOI BibTeX RDF	automated circuit synthesis, radio frequency integrated circuits, Evolutionary algorithms, analog circuit design
1	Vadim Ermolayev, Natalya Keberle, Eyck Jentzsch, Richard Sohnius, Wolf-Ekkehard Matzke	Modeling Actions in Dynamic Engineering Design Processes.	UNISCON	2009	DBLP DOI BibTeX RDF	PSI, ontology, performance, framework, task, environment, activity, action, design system
1	Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Ariana Filoramo, Christian Gamrat, Jean-Philippe Bourgoin	Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.	NanoNet	2009	DBLP DOI BibTeX RDF	Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
1	Rasmus R. Jensen, Rasmus R. Paulsen, Rasmus Larsen	Analyzing Gait Using a Time-of-Flight Camera.	SCIA	2009	DBLP DOI BibTeX RDF	computer vision, Markov random fields, gait analysis, Time-of-flight camera
1	Saeid Moslehpour, Chandrasekhar Puliroju, Akram Abu-aisheh	Design of RISC Processor Using VHDL and Cadence.	SCSS	2008	DBLP DOI BibTeX RDF
1	J. V. R. Ravindra, M. B. Srinivas	Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	krylov subspace techniques, monte-carlo simulation, model order reduction, rlc
1	Xiaolue Lai	Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia	Analog hardware implementation of a vector quantizer for focal-plane image compression.	SBCCI	2008	DBLP DOI BibTeX RDF	CMOS analog hardware, analog image processing, vector quantization
1	Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi	SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement.	ICCD	2008	DBLP DOI BibTeX RDF
1	Lukas Fujcik, Radimir Vrba, Linus Michaeli, Jiri Haze	Digital Synchronization Utilizing Harmonic Signal Generator for Capacitive Pressure Sensor Measurement.	ICONS	2008	DBLP DOI BibTeX RDF	mixed analogdigital, sensors, sigma-delta modulation
1	Yang Ran, Gavin Rosenbush, Qinfen Zheng	Computational approaches for real-time extraction of soft biometrics.	ICPR	2008	DBLP DOI BibTeX RDF
1	Kostas N. Glaros, Andreas G. Katsiamis, Emmanuel M. Drakakis	Harmonic vs. geometric mean Sinh integrators in weak inversion CMOS.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Norma Rodriguez, Li Song, Shishir Shroff, Kuang Han Chen, Taber Smith, Wilbur Luo	Hotspot Prevention Using CMP Model in Design Implementation Flow.	ISQED	2008	DBLP DOI BibTeX RDF	CMP modeling, CMP aware design, hotspot
1	Raja Bose, Abdelsalam Helal	Observing Walking Behavior of Humans Using Distributed Phenomenon Detection and Tracking Mechanisms.	SAINT	2008	DBLP DOI BibTeX RDF	Phenomena Detection and Tracking, Phenomena Clouds, Distributed Tracking, Walking Parameters, Wireless Sensor Networks, Walking
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Area efficient delay-insensitive and differential current sensing on-chip interconnect.	SoCC	2008	DBLP DOI BibTeX RDF
1	Basel Halak, Alexandre Yakovlev	Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Asynchronous operation, reliability and VLSI, Simulation, Fault tolerance, Performance, crosstalk, communication channels, Error-checking, information redundancy
1	Radu Muresan, Stefano Gregori	Protection Circuit against Differential Power Analysis Attacks for Smart Cards.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Chul-Seung Kim, Gwang-Moon Eom, K. Hase, Gon Khang, Gye Rae Tack, Jeong-Han Yi, Jae-Hoon Jun	Stimulation Pattern-Free Control of FES Cycling: Simulation Study.	IEEE Transactions on Systems, Man, and Cybernetics, Part C	2008	DBLP DOI BibTeX RDF
1	Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen	Novel Probabilistic Combinational Equivalence Checking.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Gang Qian, Jiqing Zhang, Assegid Kidané	People Identification Using Gait Via Floor Pressure Sensing and Analysis.	EuroSSC	2008	DBLP DOI BibTeX RDF	Pressure analysis, biometrics, gait recognition
1	Shuilong Huang, Huainan Ma, Zhihua Wang	Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer.	DATE	2007	DBLP DOI BibTeX RDF
1	J. V. R. Ravindra, Srinivas Bala Mandalika	Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.	SBCCI	2007	DBLP DOI BibTeX RDF	RC, distributed RLC, interconnect, SPICE, circuit, RL
1	Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan	Designing CMOS/molecular memories while considering device parameter variations.	JETC	2007	DBLP DOI BibTeX RDF	CMOS, nanotechnology, molecular electronics
1	Jan Torben Weinkopf, Klaus Harbich, Erich Barke	Incremental Fault Emulation.	FPL	2007	DBLP DOI BibTeX RDF
1	Anita Lungu, Daniel J. Sorin	Verification-Aware Microprocessor Design.	PACT	2007	DBLP DOI BibTeX RDF
1	Andreas G. Katsiamis, Henry M. D. Ip, Emmanuel M. Drakakis	A Practical CMOS Companding Sinh Lossy Integrator.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Jungseob Lee, Azadeh Davoodi	Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Ramon Tortosa Navas, Antonio Aceituno, José Manuel de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández	A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Adrian Tang 0002, Fei Yuan, Eddie Law	A New CMOS BPSK Modulator with Optimal Transaction Bandwidth Control.	ISCAS	2007	DBLP DOI BibTeX RDF
1	F. Yuan	CMOS Gyrator-C Active Transformers.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Vasilios Lirigis, Elena Dubrova	Evaluation and Comparison of Threshold Logic Gates.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Narender Hanchate, Nagarajan Ranganathan	Integrated Gate and Wire Sizing at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Yanyan Xu, Wei Chen 0018, Liang Xu, Wenhui Zhang	Evaluation of SAT-based Bounded Model Checking of ACTL Properties.	TASE	2007	DBLP DOI BibTeX RDF
1	Yi Qian, Ang Li, Qin Wang	Design and Implementation of a General Purpose Neural Network Processor.	ISNN	2007	DBLP DOI BibTeX RDF
1	Burcu Erkmen, Tülay Yildirim	CSFNN Synapse and Neuron Design Using Current Mode Analog Circuitry.	KES	2007	DBLP DOI BibTeX RDF	Conic Section Function Neural Networks, Current Mode Analog Design, Neuron and Synapse Circuitry
1	Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti	A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Mirko D'Onofrio, Niccolò Faccioli, Roberto Malagò, Giulia Zamboni, Roberto Pozzi Mucelli	Standardize and Compare Contrast-enhanced Ultrasonographic Digital Images Obtained with Different Technologies: How to Overcome the Subjectivity.	J. Digital Imaging	2007	DBLP DOI BibTeX RDF	focal liver lesion, adobe photoshop, standardization, Ultrasound, contrast-enhanced
1	Hillel Ofek	EDA vendor adoption.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud	SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers.	DAC	2006	DBLP DOI BibTeX RDF	LNA optimization, low noise amplifier, analog synthesis
1	Minghai Li, Fei Yuan	A 0.13µm CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	active inductors, class AB serial link transmitters
1	Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour	Design approaches for hybrid CMOS/molecular memory based on experimental device data.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
1	Fei Yuan	A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	Gbps serial link transmitters
1	Narender Hanchate, Nagarajan Ranganathan	A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay
1	Di Mu, Tian Xia, Hao Zheng 0001	Data Dependent Jitter Characterization Based on Fourier Analysis.	DFT	2006	DBLP DOI BibTeX RDF
1	Jan Torben Weinkopf, Klaus Harbich, Erich Barke	Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models.	FPL	2006	DBLP DOI BibTeX RDF
1	K. H. Abed, K. Y. Wong, Marian K. Kazimierczuk	CMOS zero cross-conduction low-power driver and power MOSFETs for integrated synchronous buck converter.	ISCAS	2006	DBLP DOI BibTeX RDF
1	S. Andersson, J. Dabrowski, C. Svensson, J. Konopacki	SC filter for RF down conversion with wideband image rejection.	ISCAS	2006	DBLP DOI BibTeX RDF
1	R. Barsatan, Tsz Yin Man, Mansun Chan	A zero-mask one-time programmable memory array for RFID applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti	A model for the distortion due to switch on-resistance in sample-and-hold circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	Effective capacitance of RLC loads for estimating short-circuit power.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Rong-Jian Chen, Yi-Te Lai, Jui-Lin Lai	Architecture design and VLSI hardware implementation of image encryption/decryption system using re-configurable 2D Von Neumann cellular automata.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Du Chen, Yuan Li, Dongming Xu, John G. Harris, José Carlos Príncipe	Asynchronous biphasic pulse signal coding and its CMOS realization.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Henning Gundersen, Yngvar Berg	A novel ternary more, less and equality circuit using recharged semi-floating gate devices.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Gülin Tulunay, Sina Balkir	Automatic synthesis of CMOS RF front-ends.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Zhaonian Zhang, Abdullah Celik, Paul Sotiriadis	A fast state-space algorithm to estimate harmonic distortion in fully differential weakly nonlinear Gm-C filters.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Henning Gundersen, Yngvar Berg	A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Colm McKillen, Sakir Sezer, Xin Yang	High performance service-time-stamp computation for WFQ IP packet scheduling.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Shilpa Ambarish, Mahmoud Fawzy Wagdy	A Wide-Band Digital Phase-Locked Looop.	ITNG	2006	DBLP DOI BibTeX RDF
1	Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu	CAT platform for analogue and mixed-signal test evaluation and optimization.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Anand Gautam, A. Geeta Madhuri, Priya Khandelwal, K. Pratyush Aditya, Meghana Desai, Padma N. Krishna, Malvika Dutt, Reeti Bhatia	Novel Architecture of EBC for JPEG2000.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Narender Hanchate, Nagarajan Ranganathan	A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Vagner S. Rosa, Eduardo A. C. da Costa, Sergio Bampi	A VHDL Generation Tool for Optimized Parallel FIR Filters.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann	Memory performance prediction for high-performance microprocessors at deep submicrometer technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Narender Hanchate, Nagarajan Ranganathan	Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay
1	Lee Middleton, Alex A. Buss, Alex I. Bazin, Mark S. Nixon	A Floor Sensor System for Gait Recognition.	AutoID	2005	DBLP DOI BibTeX RDF
1	Devrim Yilmaz Aksin, Franco Maloberti	Symbolic small-signal analysis (SSA) tool.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Rong-Jian Chen, Yi-Te Lai, Jui-Lin Lai	Architecture design of the re-configurable 2-D von Neumann cellular automata for image encryption application.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Ming-Ta Hsieh, Gerald E. Sobelman	Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins	A frequency up-conversion and two-step channel selection embedded CMOS D/A interface.	ISCAS	2005	DBLP DOI BibTeX RDF
1	A. Landry, Mohamed Nekili, Yvon Savaria	A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Serdar Özoguz, Nüfer Yasin Ates, Ahmed S. Elwakil	An integrated circuit chaotic oscillator and its application for high speed random bit generation.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Gülin Tulunay, Sina Balkir	Design automation of single-ended LNAs using symbolic analysis.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Nabil Abu-Khader, Pepe Siy	Multiple-Valued Logic Approach for a Systolic^2 AB Circuit in Galois Field.	ISMVL	2005	DBLP DOI BibTeX RDF