Search results for "capacitive coupling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Wen-cheng Wang, Ze-dong Nie, Feng Guan, Teng-fei Leng, Lei Wang	Experimental Studies on Human Body Communication Characteristics Based Upon Capacitive Coupling.	BSN	2011	DBLP DOI BibTeX RDF	Human body communication, channel characteristics, physiological measurements, capacitive coupling
2	Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang	Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Luís Bica Oliveira, Igor M. Filanovsky, Ahmed Allam, Jorge R. Fernandes	Synchronization of two LC- oscillators using capacitive coupling.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Jader A. De Lima	A Compact On-Chip Capacitive-Coupling Scheme for Very-Low Frequency Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Ivan C. H. Ivan Chee Hong Lai, M. Fujishima	Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems.	ASP-DAC	2007	DBLP DOI BibTeX RDF	1.2 V, pseudomillimeter-wave up-conversion mixer, vehicular radar systems, broadband up-conversion mixer, on-chip Marchand baluns, reduced substrate losses, integrated mixer, 20 to 26 GHz, 2 dB, 11.1 mW, CMOS technology, capacitive coupling, 90 nm
2	Fergal Tuffy, Liam McDaid, Vunfu Wong Kwan, John Alderman, T. Martin McGinnity, Peter M. Kelly, Jose A. Santos	Inter-Neuron Communications for Large-Scale Neural Networks using Capacitive Coupling.	IJCNN	2006	DBLP DOI BibTeX RDF
2	Amitava Bhaduri, Ranga Vemuri	Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric.	DATE	2005	DBLP DOI BibTeX RDF
2	Eugenio Culurciello, Andreas G. Andreou	Capacitive coupling of data and power for 3D silicon-on-insulator VLSI.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Jie Gu, Chris H. Kim	Multi-story power delivery for supply noise reduction and low voltage operation.	ISLPED	2005	DBLP DOI BibTeX RDF	digital voltage regulator, multi-story power delivery, supply noise, capacitive coupling
2	Puneet Gupta, Andrew B. Kahng	Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Capturing crosstalk-induced waveform for accurate static timing analysis.	ISPD	2003	DBLP DOI BibTeX RDF	capacitive coupling noise, delay calculation, slope propagation, static timing analysis, crosstalk noise
2	Yehea I. Ismail	Evaluating noise pulses in RC networks due to capacitive coupling.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Matthias Klaus, A. J. van de Goor	Tests for Resistive and Capacitive Defects in Address Decoders.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	address decoders, test conditions, Defects, opens, dynamic faults, capacitive coupling
2	Byungwoo Choi, D. M. H. Walker	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.	VTS	2000	DBLP DOI BibTeX RDF	interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
1	Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James Tschanz, Vivek De	Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Eleonora Franchi Scarselli, Antonio Gnudi, Federico Natali, Mauro Scandiuzzo, Roberto Canegallo, Roberto Guerrieri	Automatic Compensation of the Voltage Attenuation in 3-D Interconnection Based on Capacitive Coupling.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Feng Zhao, Fa Foster Dai	A 0.6V quadrature VCO with optimized capacitive coupling for phase noise reduction.	CICC	2011	DBLP DOI BibTeX RDF
1	Yang Tang, Zuochang Ye, Yan Wang	Broadband compact model for on-chip mm-wave transformers and baluns with emphasis on capacitive coupling effects.	CICC	2011	DBLP DOI BibTeX RDF
1	Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Simone Spolzino, Roberto Canegallo, L. Perilli, Roberto Cardu, Eleonora Franchi, C. Gozzi, F. Maggioni	Input/Output Pad for Direct Contact and Contactless Testing.	European Test Symposium	2011	DBLP DOI BibTeX RDF	wireless probing, I/O, SiP, capacitive coupling
1	Roberto Cardu, Eleonora Franchi, Roberto Guerrieri, Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Simone Spolzino, Roberto Canegallo	Characterization of chip-to-chip wireless interconnections based on capacitive coupling.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Mauro Scandiuzzo, Roberto Cardu, Salvatore Cani, Simone Spolzino, Luca Perugini, Eleonora Franchi, Roberto Canegallo, Roberto Guerrieri	3D system on chip memory interface based on modeled capacitive coupling interconnections.	3DIC	2010	DBLP DOI BibTeX RDF
1	Gil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai	A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems.	3DIC	2010	DBLP DOI BibTeX RDF
1	Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie	Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai	A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai	A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Roberto Cardu, Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Eleonora Franchi, Roberto Canegallo, Roberto Guerrieri	Chip-to-chip communication based on capacitive coupling.	3DIC	2009	DBLP DOI BibTeX RDF
1	Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai	A capacitive coupling interface with high sensitivity for wireless wafer testing.	3DIC	2009	DBLP DOI BibTeX RDF
1	Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee	High-speed low-power FinFET based domino logic.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Md. Sajjad Rahaman, Masud H. Chowdhury	BER performance comparison between CDMA and UWB for RF/wireless interconnect application.	EIT	2008	DBLP DOI BibTeX RDF
1	Ioannis Savidis, Eby G. Friedman	Electrical modeling and characterization of 3-D vias.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li	Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing.	ISQED	2008	DBLP DOI BibTeX RDF	Shield insertion, track routing, crosstalk optimization, global routing
1	Charbel J. Akl, Magdy A. Bayoumi	Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Cher Ming Tan, Stanny Yanuar, Tai Chong Chai	Finite element modeling of capacitive coupling voltage contrast.	Microelectronics Reliability	2007	DBLP DOI BibTeX RDF
1	Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner	Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.	ReCoSoC	2007	DBLP BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
1	Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury	Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew.	DAC	2007	DBLP DOI BibTeX RDF
1	Mustafa Emre Karagozler, Jason Campbell, Gary K. Fedder, Seth Copen Goldstein, Michael Philetus Weller, Byung Woo Yoon	Electrostatic latching for inter-module adhesion, power transfer, and communication in modular robots.	IROS	2007	DBLP DOI BibTeX RDF
1	Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury	Delay and Clock Skew Variation due to Coupling Capacitance and Inductance.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Boyan Semerdjiev, Dimitrios Velenis	Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi	Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Boyan Semerdjiev, Dimitrios Velenis	Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Martin Saint-Laurent	A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Tianpei Zhang, Sachin S. Sapatnekar	Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Mohammad Khalaj-Amirhosseini	Optimization of Microstrip Interconnects Containing Additional Capacitive Coupling Using Least Mean Square Method.	Journal of Circuits, Systems, and Computers	2006	DBLP DOI BibTeX RDF
1	C. M. Tan, M. H. Chowdhury	Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Itisha Chanodia, Dimitrios Velenis	Effects of crosstalk noise on H-tree clock distribution networks.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Eugenio Culurciello, Andreas G. Andreou	3D integrated sensors in silicon-on-sapphire CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Erhan Ozalevli, Paul E. Hasler	A tunable floating gate CMOS resistor for low-power and low-voltage applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas	A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Usha Narasimha, Binu Abraham, N. S. Nagaraj	Statistical Analysis of Capacitance Coupling Effects on Delay and Noise.	ISQED	2006	DBLP DOI BibTeX RDF
1	Itisha Chanodia, Dimitrios Velenis	Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Shweta Chary, Michael L. Bushnell	Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Shweta Chary, Michael L. Bushnell	Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De	Formal derivation of optimal active shielding for low-power on-chip buses.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn	Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	S. Kolberg, Tor A. Fjeldly, Benjamín Iñíguez	Self-consistent 2D Compact Model for Nanoscale Double Gate MOSFETs.	International Conference on Computational Science	2006	DBLP DOI BibTeX RDF
1	Saihua Lin, Huazhong Yang	Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Payam Heydari, Massoud Pedram	Capacitive coupling noise in high-speed VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Eng Chong Tan, Abdul Wahab, Kay Min Low	Application of capacitive coupling to the design of an absolute-coordinate pointing device.	IEEE T. Instrumentation and Measurement	2005	DBLP DOI BibTeX RDF
1	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity
1	Krishnan Sundaresan, Nihar R. Mahapatra	Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.	HPCA	2005	DBLP DOI BibTeX RDF
1	Vishal Gupta, Gabriel A. Rincón-Mora	A low dropout, CMOS regulator with high PSR over wideband frequencies.	ISCAS	2005	DBLP DOI BibTeX RDF
1	S. B. Prakash, Pamela Abshire, M. Urdaneta, Elisabeth Smela	A CMOS capacitance sensor for cell adhesion characterization.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan	A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries.	ISQED	2005	DBLP DOI BibTeX RDF
1	Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.	ISQED	2005	DBLP DOI BibTeX RDF
1	Gaurav Kumar Varshney, Sreeram Chandrasekar	An Efficient Methodology for Noise Characterization.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester	Switch-factor based loop RLC modeling for efficient timing analysis.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Bruce Randall Donald, Christopher G. Levey, Craig D. McGray, Igor Paprotny, Daniela Rus	A Steerable, Untethered, 250 × 60µm MEMS Mobile Micro-Robot.	ISRR	2005	DBLP DOI BibTeX RDF
1	Young-Jun Lee, Yong-Bin Kim	A fast and precise interconnect capacitive coupling noise model.	ISCAS	2004	DBLP BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail	Formal derivation of optimal active shielding for low-power on-chip buses.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Liang Deng, Martin D. F. Wong	Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus.	DATE	2004	DBLP DOI BibTeX RDF
1	Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	A Crosstalk Aware Interconnect with Variable Cycle Transmission.	DATE	2004	DBLP DOI BibTeX RDF
1	Craig Petrie, Tianxue Sun, Matt Miller	A high-gain offset-compensated differential amplifier.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Xiaoliang Bai, Sujit Dey	High-level crosstalk defect Simulation methodology for system-on-chip interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo	Probabilistic crosstalk delay estimation for ASICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Markus Tahedl, Hans-Jörg Pfleiderer	Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
1	Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi	CodSim -- A Combined Delay Fault Simulator.	DFT	2003	DBLP DOI BibTeX RDF
1	Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu	On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Puneet Gupta, Andrew B. Kahng	Quantifying Error in Dynamic Power Estimation of CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
1	Paolo Pavan, Luca Larcher, Massimiliano Cuozzo, Paola Zuliani, Antonino Conte	A complete model of E2PROM memory cells for circuit simulations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	O. Milter, Avinoam Kolodny	Crosstalk noise reduction in synthesized digital logic circuits.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Bruce Randall Donald, Christopher G. Levey, Craig D. McGray, Daniela Rus, Mike Sinclair	UntetheredMicro-Actuators for Autonomous Micro-robot Locomotion: Design, Fabrication, Control, and Performance.	ISRR	2003	DBLP DOI BibTeX RDF
1	Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal	Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.	ITC	2002	DBLP DOI BibTeX RDF
1	Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul	Estimation of the likelihood of capacitive coupling noise.	DAC	2002	DBLP DOI BibTeX RDF	noise, signal integrity, deep submicron
1	Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera	Crosstalk noise optimization by post-layout transistor sizing.	ISPD	2002	DBLP DOI BibTeX RDF	capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise
1	Tao Lin, Michael W. Beattie, Lawrence T. Pileggi	On the efficacy of simplified 2D on-chip inductance models.	DAC	2002	DBLP DOI BibTeX RDF	PEEC, on-chip inductance, sparsified model
1	Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw	Estimation of signal arrival times in the presence of delay noise.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Lauren Hui Chen, Malgorzata Marek-Sadowska	Closed-Form Crosstalk Noise Metrics for Physical Design Applications.	DATE	2002	DBLP DOI BibTeX RDF
1	Lauren Hui Chen, Malgorzata Marek-Sadowska	Efficient Closed-Form Crosstalk Delay Metrics. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	interconnect coupling, coupling direction, delay, crosstalk
1	Rahul Kundu, R. D. (Shawn) Blanton	Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits.	VTS	2002	DBLP DOI BibTeX RDF
1	Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer	Analytical models for crosstalk excitation and propagation in VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Payam Heydari, Massoud Pedram	Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits.	ICCD	2001	DBLP BibTeX RDF
1	Paul-Peter Sotiriadis, Anantha Chandrakasan	Reducing bus delay in submicron technology using coding.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Soha Hassoun	Critical path analysis using a dynamically bounded delay model.	DAC	2000	DBLP DOI BibTeX RDF
1	J. A. Sainz, R. Muñoz, J. A. Maiz, L. A. Aguado, Miquel Roca	A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits.	IOLTW	2000	DBLP DOI BibTeX RDF	VLSI, Sensor, CMOS, Crosstalk, Digital
1	Kathirgamar Aingaran, Fabian Klass, Chin-Man Kim, Chaim Amir, Joydeep Mitra, Eileen You, Jamil Mohd, Sai-keung Dong	Coupling Noise Analysis for VLIS and ULSI Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Crosstalk Analysis, Crosstalk Modeling, Noise
1	Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen	An Automated Shielding Algorithm and Tool For Dynamic Circuits.	ISQED	2000	DBLP DOI BibTeX RDF
1	J. Briaire, K. S. Krisch	Principles of substrate crosstalk generation in CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	B. E. Duewer, J. M. Wilson, D. A. Winick, Paul D. Franzon	MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications.	ARVLSI	1999	DBLP DOI BibTeX RDF	Variable Capacitors, Programable Interconnect, RF Switching, Digital Switching, Bistable Devices, MEMS, Crossbar, Capacitive Coupling