Search results for "carry-select adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Sun Yan, Zhang Xin, Jin Xi	High-Performance Carry Select Adder Using Fast All-One Finding Logic.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	fast all-one finding circuit, add-one circuit, carry-select adder
3	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld	Modulo p=3 Checking for a Carry Select Adder.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	concurrent checking, modulo checking, carry select adder
3	Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh	Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, carry-select adder
3	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy	Low-power carry-select adder using adaptive supply voltage based on input vector patterns.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive supply voltage, low power adder, carry-select adder
2	Alireza Namazi, Seyed Ghassem Miremadi, Alireza Ejlali	A High Speed and Low Cost Error Correction Technique for the Carry Select Adder.	ARES	2009	DBLP DOI BibTeX RDF
2	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.	ISQED	2005	DBLP DOI BibTeX RDF
2	Yajuan He, Chip-Hong Chang, Jiangmin Gu	An area efficient 64-bit square root carry-select adder for low power applications.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Dilip P. Vasudevan, Parag K. Lala	A Technique for Modular Design of Self-Checking Carry-Select Adder.	DFT	2005	DBLP DOI BibTeX RDF
2	Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.	DATE	2004	DBLP DOI BibTeX RDF
2	Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel	Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits.	IOLTS	2004	DBLP DOI BibTeX RDF
2	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld	A Modulo p Checked Self-Checking Carry Select Adder.	IOLTS	2003	DBLP DOI BibTeX RDF
2	Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner	Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	SOI technology, logic design styles, circuit Design
2	Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim	A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy	High performance and low power FIR filter design based on sharing multiplication.	ISLPED	2002	DBLP DOI BibTeX RDF	FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder
2	Youngjoon Kim, Lee-Sup Kim	A low power carry select adder with reduced area.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Nobutaka Kito, Shinichi Fujii, Naofumi Takagi	A C-Testable Multiple-Block Carry Select Adder.	IEICE Transactions	2012	DBLP BibTeX RDF
1	B. Ramkumar, Harish M. Kittur	Low-Power and Area-Efficient Carry Select Adder.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, Khayrollah Hadidi, Abdollah Khoei, Pourya Hoseini	High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder.	ICECS	2011	DBLP DOI BibTeX RDF
1	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition.	ISQED	2009	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima	ROM based logic (RBL) design: High-performance and low-power adders.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien	Performance comparison of quantum-dot cellular automata adders.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Gustavo A. Ruiz, Mercedes Granda	An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit.	Microelectronics Journal	2004	DBLP DOI BibTeX RDF
1	Asim J. Al-Khalili, Aiping Hu	Design of a 32-bit squarer - exploiting addition redundancy.	ISCAS	2003	DBLP DOI BibTeX RDF
1	B. Kiran Kumar, Parag K. Lala	On-line Detection of Faults in Carry-Select Adders.	ITC	2003	DBLP DOI BibTeX RDF
1	M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu	A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka	A fast hybrid carry-lookahead/carry-select adder design.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	CMOS, domino logic, carry lookahead adder
1	Amaury Nève, Denis Flandre	Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies.	VLSI-SOC	2001	DBLP BibTeX RDF
1	Mircea R. Stan	Synchronous Up/Down Counter with Clock Period Independent of Counter Size.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	up/down counters, constant time counters, prescalers
1	Hanho Lee, Gerald E. Sobelman	A New Low-Voltage Full Adder Circuit.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
1	M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf	The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
1	M. Shamanna, Sterling R. Whitaker	A Carry Select Adder with Conflict Free Bypass Circuit.	VLSI Design	1993	DBLP BibTeX RDF
1	Jalil Fadavi-Ardekani	M×N Booth encoded multiplier generator using optimized Wallace trees.	IEEE Trans. VLSI Syst.	1993	DBLP DOI BibTeX RDF