Search results for "cellular arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	A cellular array designed from a Multiple-valued Decision Diagram and its fault tests.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults
2	Jia Di, Parag K. Lala	Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Reed-Muller expression, nanoscale circuit, layout, stuck-at fault, cellular arrays, delay-insensitive circuit
2	Jia Di, Dilip P. Vasudevan	Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.	DELTA	2006	DBLP DOI BibTeX RDF
2	Hiroshi Umeo, Masaya Hisaoka, Shunsuke Akiguchi	A Twelve-State Optimum-Time Synchronization Algorithm for Two-Dimensional Rectangular Cellular Arrays.	UC	2005	DBLP DOI BibTeX RDF
2	Pasquale Corsonello, Stefania Perri, G. Cororullo	Area-time-power tradeoff in cellular arrays VLSI implementations.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Vishwani D. Agrawal	Comments on ``An Approach to Highly Integrated Computer-Maintained Cellular Arrays''.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	faults in logic arrays, percolation process, Cellular arrays, random processes, programmable logic
2	Frank B. Manning	An Approach to Highly Integrated, Computer-Maintained Cellular Arrays.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	computer maintenance, self-repairing machines, fault-tolerance, reliability, very large-scale integration, Cellular arrays, programmable logic
2	J. A. Bate, Jon C. Muzio	Three Cell Structures for Ternary Cellular Arrays.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	combinational switching functions, ternary full adder, universal arrays, Cellular arrays, symmetric functions, ternary logic
1	Hiroshi Umeo	Realizing Global Synchronizations for Locally-Connected Two-Dimensional Rectangle Cellular Arrays.	AINA	2012	DBLP DOI BibTeX RDF
1	Xiao-dong Sun, Hong-bin Zhang	A Fast Hole-filling Strategy of 3D Scanned Human Body.	CGIV	2009	DBLP DOI BibTeX RDF
1	Josep Carmona, Jordi Cortadella, Yousuke Takada, Ferdinand Peper	Formal methods for the analysis and synthesis of nanometer-scale cellular arrays.	JETC	2008	DBLP DOI BibTeX RDF	model checking, cellular array, Nanocomputing, symbolic techniques
1	Hiroshi Umeo	Time-Optimum Synchronization Algorithms for Two-Dimensional Cellular Arrays - A Survey.	IICAI	2007	DBLP BibTeX RDF
1	Hiroshi Umeo, Takuya Yamawaki, Naoki Shimizu, Hiroki Uchino	Modeling and Simulation of Global Synchronization Processes for Large-Scale-of Two-Dimensional Cellular Arrays.	Asia International Conference on Modelling and Simulation	2007	DBLP DOI BibTeX RDF
1	Hiroshi Umeo, Hiroki Uchino	A New Time-Optimum Synchronization Algorithm for Two-Dimensional Cellular Arrays.	EUROCAST	2007	DBLP DOI BibTeX RDF
1	Yuan Zhang, Youren Wang, Shanshan Yang, Min Xie	Design of a Cell in Embryonic Systems with Improved Efficiency and Fault-Tolerance.	ICES	2007	DBLP DOI BibTeX RDF	Embryonic systems, Two-level self-repair, Extended hamming code, Fault tolerance of configuration memory, Cellular arrays
1	Hiroshi Umeo, Masashi Maeda, Kazuaki Hongyo	A Design of Symmetrical Six-State 3n-Step Firing Squad Synchronization Algorithms and Their Implementations.	ACRI	2006	DBLP DOI BibTeX RDF
1	Boris D. Lubachevsky	Efficient Parallel Simulations of Asynchronous Cellular Arrays	CoRR	2005	DBLP BibTeX RDF
1	Alberto Gallini, Claudio Ferretti, Giancarlo Mauri	Bio Molecular Engine: a bio-inspired environment for models of growing and evolvable computation.	GECCO Workshops	2005	DBLP DOI BibTeX RDF	simulation software, scalability, evolutionary algorithms, computer architectures, cellular arrays
1	Jia Di, Parag K. Lala, Dilip P. Vasudevan	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.	DFT	2005	DBLP DOI BibTeX RDF
1	Olga L. Bandman	Composing Fine-Grained Parallel Algorithms for Spatial Dynamics Simulation.	PaCT	2005	DBLP DOI BibTeX RDF
1	Olga L. Bandman	Algebraic Properties of Cellular Automata: The Basis for Composition Technique.	ACRI	2004	DBLP DOI BibTeX RDF
1	Hiroshi Umeo, Masaya Hisaoka, Takashi Sogabe	A Comparative Study of Optimum-Time Synchronization Algorithms for One-Dimensional Cellular Automata - A Survey.	ACRI	2004	DBLP DOI BibTeX RDF
1	Hiroshi Umeo, Masaya Hisaoka, Masato Teraoka, Masashi Maeda	Several New Generalized Linear- and Optimum-Time Synchronization Algorithms for Two-Dimensional Rectangular Arrays.	MCU	2004	DBLP DOI BibTeX RDF
1	Hiroshi Umeo, Masaya Hisaoka, Takashi Sogabe	A Comparative Investigation into Optimum-Time Synchronization Protocols for a Large Scale of One-Dimensional Cellular Automata.	ISPA	2003	DBLP DOI BibTeX RDF
1	Olga L. Bandman	Accuracy and Stability of Spatial Dynamics Simulation by Cellular Automata Evolution.	PaCT	2003	DBLP DOI BibTeX RDF
1	Hiroshi Umeo, Masashi Maeda, Norio Fujiwara	An Efficient Mapping Scheme for Embedding Any One-Dimensional Firing Squad Synchronization Algorithm onto Two-Dimensional Arrays.	ACRI	2002	DBLP DOI BibTeX RDF
1	Yuri Velinov	On the Software Design of Cellular Automata Simulators for Ecological Modeling.	CIAA	2001	DBLP DOI BibTeX RDF
1	Alexander L. Wijesinha, Srikanta P. Kumar, Deepinder P. Sidhu	Handover and new call blocking performance with dynamic single-channel assignment in linear cellular arrays.	Wireless Networks	2000	DBLP DOI BibTeX RDF
1	Martin Kutrib, Jan-Thomas Löwe	Massively Parallel Pattern Recognition with Link Failures.	SOFSEM	2000	DBLP DOI BibTeX RDF
1	Dhiraj K. Pradhan, Mitrajit Chatterjee	GLFSR-a new test pattern generator for built-in-self-test.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Thomas Buchholz, Andreas Klein, Martin Kutrib	One Guess One-Way Cellular Arrays.	MFCS	1998	DBLP DOI BibTeX RDF
1	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	On Design of Fail-Safe Cellular Arrays.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	fail-safe logic system, Binary Decision Diagram and switch cell, cellular array
1	Jitendra Khare, Wojciech Maly, Nathan Tiday	Fault characterization of standard cell libraries using inductive contamination.	VTS	1996	DBLP DOI BibTeX RDF	surface contamination, fault characterization, standard cell libraries, inductive contamination analysis, contamination diagnosis, gate-level delay characterization, fault diagnosis, test generation, integrated circuit testing, cellular arrays, defect coverage
1	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
1	Naotake Kamiura, Hidetoshi Satoh, Yutaka Hata, Kazuharu Yamato	On Ternary Cellular Arrays Designed from Ternary Decision Diagrams.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
1	Valentina P. Markova	Multilayer Cellular Algorithm for Complex Number Multiplication.	ASAP	1995	DBLP DOI BibTeX RDF	Knuth number system, 3D cellular arrays, Parallel Substitution Algorithm, distributed computations, complex multiplication
1	Kees van Berkel, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel	A single-rail re-implementation of a DCC error detector using a generic standard-cell library.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, DCC error detector, generic standard-cell library, single-rail re-implementation, fully asynchronous implementation, handshake signaling, single-rail data encoding, generic cell library, high-level Tangram description, intermediate architecture, high level synthesis, asynchronous circuits, error detection codes, integrated logic circuits, cellular arrays, power dissipation, handshake circuits
1	Ad M. G. Peeters, Kees van Berkel	Single-rail handshake circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays
1	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
1	Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten	Performance driven standard-cell placement using the genetic algorithm.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement
1	Khushro Shahookar, Pinaki Mazumder	Genetic multiway partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	genetic multiway partitioning, result quality, binary chromosome, bit-mask operations, net cut evaluation, MCNC benchmark circuits, cut size, genetic algorithms, VLSI, VLSI, CAD, software tools, software tool, logic CAD, mutation, circuit CAD, crossover, cellular arrays, cost function, circuit optimisation, logic partitioning, multiple objectives, bipartitioning
1	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
1	Andrej Zemva, Franc Brglez	Detectable perturbations: a paradigm for technology-specific multi-fault test generation.	VTS	1995	DBLP DOI BibTeX RDF	detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
1	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Design of Fault-Tolerant Cellular Arrays on Multiple-Valued Logic.	ISMVL	1994	DBLP BibTeX RDF
1	Oscar H. Ibarra, Tao Jiang	On Some Open Problems Concerning the Complexity of Cellular Arrays.	Results and Trends in Theoretical Computer Science	1994	DBLP DOI BibTeX RDF
1	K. P. Lam, Ed. Horne	On Integrating the BWS and FWS Classifiers: A Parallel Approach for Image Classification Using Cellular Arrays of Memory.	PARCO	1993	DBLP BibTeX RDF
1	Naotake Kamiura, Yutaka Hata, Fujio Miyawaki, Kazuharu Yamato	Easily Testable Multiple-Valued Cellular Arrays.	ISMVL	1992	DBLP BibTeX RDF
1	De-Lei Lee	Architecture of an Array Processor Using a Nonlinear Skewing Scheme.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	nonlinear skewing scheme, array processor architecture, interconnection network, parallel architectures, multiprocessor interconnection networks, cellular arrays, array processor, skewing schemes
1	Cheng-Wen Wu, Shyue-Kung Lu	Designing Self-Testable Cellular Arrays.	ICCD	1991	DBLP BibTeX RDF
1	Çetin Kaya Koç, Ching Yu Hung	Bit-level systolic arrays for modular multiplication.	VLSI Signal Processing	1991	DBLP DOI BibTeX RDF	sign estimation, scheduling, systolic array, modular multiplication, carry save adders
1	Ferng-Ching Lin, Kung Chen	On the Design of a Unidirectional Systolic Array for Key Enumeration.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	unidirectional systolic array, key enumeration, unidirectional data flow, maximum data pipelining rate, closest-neighbor problems, design, computational geometry, computational geometry, cellular arrays
1	A. Majumdar, C. S. Raghavendra, Melvin A. Breuer	Fault Tolerance in Linear Systolic Arrays Using Time Redundancy.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	triple time redundancy, gracefully degradable mode, fault tolerant computing, logic testing, reconfiguration, throughput, interconnection, switching, performance metrics, cellular arrays, running time, reliability analysis, control structures, fault-tolerant capabilities, linear systolic arrays
1	P. C. Mathias, Lalit M. Patnaik	Systolic Evaluation of Polynomial Expressions.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	systolic evaluation, polynomial expressions, frame buffers, single wavefront complex cell array, multiple wavefront array, VLSI, computer graphics, computer graphics, interconnection, polynomials, cellular arrays, VLSI implementation
1	Cheng-Wen Wu, Peter R. Cappello	Easily Testable Iterative Logic Arrays.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	easily testable iterative logic arrays, octagonally connected arrays, combinational arrays, inhomogeneous arrays, bilateral arrays, test complexity, pipelined arrays, logic testing, systolic arrays, upper bound, matrix multiplication, cellular arrays, combinatorial circuits, multidimensional arrays
1	Oscar H. Ibarra, Stephen M. Sohn	On Mapping Systolic Algorithms onto the Hypercube.	IEEE Trans. Parallel Distrib. Syst.	1990	DBLP DOI BibTeX RDF	parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation
1	PeiZong Lee, Zvi M. Kedem	Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays.	IEEE Trans. Parallel Distrib. Syst.	1990	DBLP DOI BibTeX RDF	nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation
1	Ahmed El-Amawy	A Systolic Architecture for Fast Dense Matrix Inversion.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fast dense matrix inversion, data-steering technique, feedback recurrences, VLSI, cellular arrays, Gaussian elimination, systolic architecture, VLSI algorithms, computerised signal processing
1	H. V. Jagadish, Thomas Kailath	A Family of New Efficient Arrays for Matrix Multiplication.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	regular iterative algorithm, matrix multiplication arrays, iteration vector, conventional arrays, processor cells, iterative methods, matrix algebra, cellular arrays, multiplying circuits
1	Viktor K. Prasanna, Yu-Chen Tsai	On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant systolic arrays, linearly connected arrays, processor elements, VLSI model, Diogenes methodology, algorithms, fault tolerant computing, cellular arrays, propagation delay, matrix computations, mapping technique, linear systolic arrays
1	Clement Wing Hong Lam, Hon Fung Li, R. Jayakumar	A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	faulty systolic arrays, faulty cells, square array, minimal fault pattern, fault tolerance, fault tolerant computing, redundancy, redundancy, cellular arrays
1	Hon Fung Li, R. Jayakumar, Clement Wing Hong Lam	Restructuring for Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant systolic arrays, faulty cells, data-flow paths, computational sites, programmable delays, fault tolerant computing, cellular arrays, restructuring, processing elements, data skewing
1	Rami G. Melhem	A Systolic Accelerator for the Iterative Solution of Sparse Linear Systems.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	stripe structures, preconditioned conjugate gradient, iterative solution, nonzero elements, systolic accelerator, computationally irregular problems, systolic networks, parallel processing, iterative methods, systolic arrays, matrix algebra, buffering, cellular arrays, sparse matrix, special purpose computers, sparse linear systems, data movement
1	A. Yavuz Oruç, Ajai Thirumalai	A Systematic Design of Cellular Permutation Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	cellular permutation arrays, coset decompositions, permutation cell, coset generator, target network, multiprocessor interconnection networks, network topology, cellular arrays, cost function, propagation delay, fan-out, fan-in
1	Oscar H. Ibarra, Tao Jiang	Relating the Power of Cellular Arrays to Their Closure Properties.	Theor. Comput. Sci.	1988	DBLP DOI BibTeX RDF
1	Nandor Toth	Self-checking processing elements in cellular arrays.	Parcella	1988	DBLP DOI BibTeX RDF
1	Peter R. Cappello, Willard L. Miranker	Systolic Super Summation.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	systolic super summer, cellular design, summands, fixed-point form, cellular packet-switching device, VLSI, digital arithmetic, floating-point arithmetic, cellular arrays, accumulators, synchronous model
1	Yoon-Hwa Choi, Miroslaw Malek	A Fault-Tolerant Systolic Sorter.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	VLSI sorter, fault-tolerant systolic sorter, permanent computation errors, error-checking code, redundant cells, single faulty cell, offline fault-testing, permanent stuck-at faults, testing, fault tolerant computing, reconfiguration, redundancy, integrated circuit testing, sorting, automatic testing, invariants, error detection codes, cellular arrays, algorithm-based fault tolerance, digital integrated circuits, hardware overhead, time overhead
1	David K. Probst, Hon Fung Li	Abstract Specification of Synchronous Data Types for VLSI and Proving the Correctness of Systolic Network Implementations.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	correctness proving, abstract specification, synchronous data types, systolic network implementations, Parnas trace method, VLSI, VLSI, data structures, data flow, control flow, cellular arrays, software modules
1	Adit D. Singh	Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	area efficient fault tolerance scheme, large area VLSI processor arrays, interstitial sites, operational spares, area efficient layouts, chip area utilization, interstitial redundancy, PE survival probabilities, VLSI, fault tolerant computing, reconfiguration, redundancy, polynomial time algorithm, cellular arrays, switching network, performance degradation, wafer scale integration, circuit layout
1	Bing Bing Zhou	A New Bit-Serial Systolic Multiplier Over GF(2m).	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	bit-serial systolic multiplier, VLSI, logic design, cellular arrays, linear systolic array
1	Oscar H. Ibarra, Tao Jiang	On One-Way Cellular Arrays.	SIAM J. Comput.	1987	DBLP DOI BibTeX RDF
1	Oscar H. Ibarra, Tao Jiang	On the Computing Power of One-Way Cellular Arrays.	ICALP	1987	DBLP DOI BibTeX RDF
1	M. Ladjadj, J. F. McDonald, D.-H. Ho, W. Murray	Use of the subscripted DALG in submodule testing with applications in cellular arrays.	DAC	1986	DBLP DOI BibTeX RDF
1	Myoung Sung Lee, Gideon Frieder	Massively Fault-Tolerant Cellular Arrays.	ICPP	1986	DBLP BibTeX RDF
1	Zdenek Zdráhal, Ivan Bratko, Alen Shapiro	Recognition of Complex Patterns Using Cellular Arrays.	Comput. J.	1981	DBLP DOI BibTeX RDF
1	Jan Gecsei	Interconnection Networks from Three-State Cells.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	partition networks, Cellular arrays, switching networks
1	Chia-Hsiaing Sung	Testable Sequential Cellular Arrays.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF
1	Jayanti C. Majithia	Some Comments Concerning Design of Pipeline Arithmetic Arrays.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	parallel processes, pipelining, Cellular arrays, figure of merit
1	Antonio Grasselli	Synchronization of Cellular Arrays: The Firing Squad Problem in Two Dimensions	Information and Control	1975	DBLP DOI BibTeX RDF
1	Gabor T. Herman, Wu-Hang Liu, Stuart W. Rowland, Adrian Walker	Synchronization of Growing Cellular Arrays	Information and Control	1974	DBLP DOI BibTeX RDF
1	Karl N. Levitt, William H. Kautz	Cellular Arrays for the Solution of Graph Problems.	Commun. ACM	1972	DBLP DOI BibTeX RDF
1	D. A. Stern, Hwa C. Torng	NAND Cellular Arrays	SWAT (FOCS)	1971	DBLP DOI BibTeX RDF
1	Robert C. Minnick	A Survey of Microcellular Research.	J. ACM	1967	DBLP DOI BibTeX RDF