Search results for "charge-recycling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Kimish Patel, Wonbok Lee, Massoud Pedram	In-order pulsed charge recycling in off-chip data buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	data buses, power, charge recycling
3	Zhiyu Liu, Volkan Kursun	Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.	ISQED	2007	DBLP DOI BibTeX RDF	Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling
3	Keejong Kim, Hamid Mahmoodi, Kaushik Roy	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
3	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge recycling in MTCMOS circuits: concept and analysis.	DAC	2006	DBLP DOI BibTeX RDF	low power design, MTCMOS, charge recycling
2	Zhiyu Liu, Volkan Kursun	Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Ka-Ming Keung, Akhilesh Tyagi	SRAM CP: A Charge Recycling Design Schema for SRAM.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa	High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Keejong Kim, Chris H. Kim, Kaushik Roy	TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.	ISQED	2005	DBLP DOI BibTeX RDF
2	Byung-Do Yang, Lee-Sup Kim	A low-power charge-recycling ROM architecture.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Ali Abbasian, S. H. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani	No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Peter Celinski, Derek Abbott, Sorin Dan Cotofana	Area efficient, high speed parallel counter circuits using charge recycling threshold logic.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López	Low depth carry lookahead addition using charge recycling threshold logic.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Byung-Do Yang, Lee-Sup Kim	A low power charge-recycling ROM architecture.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Jouko Marjonen, Markku Åberg	A Single Clocked Adiabatic Static Logic - A Proposal for Digital Low Power Applications.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	sinisoidal power source, non-existing DC-path, load capacitance, LC-oscillator, charge recycling
2	Seung-Moon Yoo, Sung-Mo Kang	No-Race Charge-Recycling Differential Logic (NCDL).	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
2	Xiaohui Wang, Wolfgang Porod	A Low Power Charge-Recycling CMOS Clock Buffer.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
2	Seung-Moon Yoo, Sung-Mo Kang	CMOS Pass-gate No-race Charge-recycling Logic (CPNCL).	ISCAS	1999	DBLP DOI BibTeX RDF
1	Byung-Do Yang	A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Xu Wang, Jian-Fei Jiang, Zhi-Gang Mao, Bingjing Ge, Xinglong Zhao	A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme.	ICECS	2011	DBLP DOI BibTeX RDF
1	Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel	Charge Recycling in Voltage-Dithered Circuits.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Katsumi Dosaka, Daisuke Ogawa, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda	A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Byung-Do Yang	A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi	High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic.	DSD	2009	DBLP DOI BibTeX RDF
1	Jianwei Zhang, Yizheng Ye, Bin-Da Liu, Feng Guan	Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge Recycling in Power-Gated CMOS Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ka-Ming Keung, Vineela Manne, Akhilesh Tyagi	A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Dan Li, Tingcun Wei, Wei Wu	A novel charge recycler for TFT-LCD source driver IC.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	dot-inversion, source driver, space correlation, time correlation, TFT-LCD, charge recycler
1	Brian P. Ginsburg, Anantha P. Chandrakasan	An energy-efficient charge recycling approach for a SAR converter with capacitive DAC.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Kris Tiri, Ingrid Verbauwhede	Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security ICs against Differential Power Analysis.	IACR Cryptology ePrint Archive	2004	DBLP BibTeX RDF
1	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis	Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Peter Celinski, Derek Abbott, Sorin Cotofana	Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Vineela Manne, Akhilesh Tyagi	An Adiabatic Charge Pump Based Charge Recycling Design Style.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Saravanan Rajapandian, Zheng Xu, Kenneth L. Shepard	Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
1	Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong	A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Paul-Peter Sotiriadis, Theodoros Konstantakopoulos, Anantha Chandrakasan	Analysis and implementation of charge recycling for deep sub-micron buses.	ISLPED	2001	DBLP DOI BibTeX RDF
1	K. Y. Cheung	CRRDL: a novel charge recovery-recycling differential logic.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Hongchin Lin, Yi-Fan Chen, Hsien-Chih She	A low-power 3-phase half rail pass-gate differential logic.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Spiridon Nikolaidis, Efstathios D. Kyriakis-Bitzaros	A Charge Recycling Technique for the Design of Low Power CMOS Clock Drivers.	Journal of Circuits, Systems, and Computers	1999	DBLP DOI BibTeX RDF