Search results for "chip multi processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Deng Yadan, Jing Ning, Xiong Wei, Chen Luo, Chen Hongsheng	Hash Join Optimization Based on Shared Cache Chip Multi-processor.	DASFAA	2009	DBLP DOI BibTeX RDF	Radix-Join, Shared L2-Cache, Chip Multi-Processor, Cache Conflict
2	Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin	Scaling the bandwidth wall: challenges in and avenues for CMP scaling.	ISCA	2009	DBLP DOI BibTeX RDF	analytical model, memory bandwidth, chip multi-processor
2	Sushu Zhang, Karam S. Chatha	Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Tang	Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor.	DATE	2008	DBLP DOI BibTeX RDF
2	Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga	Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, Daniel A. Connors	Chip multi-processor scalability for single-threaded applications.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
2	Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin	Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture.	HPCA	2005	DBLP DOI BibTeX RDF
2	Bart D. Theelen, A. C. Verschueren	Architecture Design of a Scalable Single-Chip Multi-Processor.	DSD	2002	DBLP DOI BibTeX RDF
1	Lionel Damez, Loic Sieler, Alexis Landrault, Jean-Pierre Dérutin	Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach.	J. Real-Time Image Processing	2011	DBLP DOI BibTeX RDF
1	Zheng Lv, Hao Chen, Feng Chen, Yi Lv	Fast Verification of Memory Consistency for Chip Multi-Processor.	CIS	2011	DBLP DOI BibTeX RDF
1	Chi Zhang, Xiang Wang	On Chip Cache Quantitative Optimization Approach: Study in Chip Multi-processor Design.	HPCA (China)	2009	DBLP DOI BibTeX RDF
1	Jinwoo Song, Kee Beom Kim, Yong Ho Song, Ki-Seok Chung	Implementation of IEEE802.11a software defined receiver on chip multi-processor architecture using OpenMP.	ICHIT	2009	DBLP DOI BibTeX RDF	802.11a, GPP, multi-core, OpenMP, SDR
1	Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser	Multiple clock and voltage domains for chip multi processors.	MICRO	2009	DBLP DOI BibTeX RDF	clock domains, voltage domain, power management, DVFS, chip multi processor
1	Ravi Iyer, Ramesh Illikkal, Li Zhao, Don Newell, Jaideep Moses	Virtual platform architectures for resource metering in datacenters.	SIGMETRICS Performance Evaluation Review	2009	DBLP DOI BibTeX RDF
1	Lei Shi, Jun Pang, Lei Yang, Tiejun Zhang, Donghui Wang	Fair-Priority-Expression-Based burst scheduling to enhance performance and fairness of shared dram systems.	CCECE	2009	DBLP DOI BibTeX RDF
1	Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan	Fast complete memory consistency verification.	HPCA	2009	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi	Adaptive Spill-Receive for robust high-performance caching in CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Sudipto Das, Shyam Antony, Divyakant Agrawal, Amr El Abbadi	CoTS: A Scalable Framework for Parallelizing Frequency Counting over Data Streams.	ICDE	2009	DBLP DOI BibTeX RDF
1	Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang	NBTI aware workload balancing in multi-core systems.	ISQED	2009	DBLP DOI BibTeX RDF
1	Ghiath Al-Kadi, Andrei Sergeevich Terechko	A Hardware Task Scheduler for Embedded Video Processing.	HiPEAC	2009	DBLP DOI BibTeX RDF	Hardware task scheduler, task dependency patterns, H.264 video compression, embedded video processing
1	Jean-Pierre Dérutin, Lionel Damez, Alexis Landrault	Embedding of a Real Time Image Stabilization Algorithm on SoPC Platform, a Chip Multi-processor Approach.	ACIVS	2008	DBLP DOI BibTeX RDF
1	Hiroaki Nishikawa, Hiroshi Tomiyasu, Hiroyuki Uchida	VLSI Design of Networking-Oriented Chip Multi-Processor; CUE-v3.	PDPTA	2008	DBLP BibTeX RDF
1	Ke Meng, Russ Joseph, Robert P. Dick, Li Shang	Multi-optimization power management for chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	cache resizing, voltage/frequency scaling, dynamic power management, chip multi-processor
1	Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas	Architecture and Evaluation of an Asynchronous Array of Simple Processors.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
1	Wolfgang Puffitsch	Decoupled root scanning in multi-processor systems.	CASES	2008	DBLP DOI BibTeX RDF	real-time, garbage collection, multi-processor
1	Song Hao, Zhihui Du, David A. Bader, Man Wang	A Prediction Based CMP Cache Migration Policy.	HPCC	2008	DBLP DOI BibTeX RDF
1	Aditya Yanamandra, Bryan Cover, Padma Raghavan, Mary Jane Irwin, Mahmut T. Kandemir	Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations.	IPDPS	2008	DBLP DOI BibTeX RDF
1	A. Elyada, Ran Ginosar, Uri C. Weiser	Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Samy Makar, Tony Altinis, Niteen Patkar, Janet Wu	Testing of Vega2, a chip multi-processor with spare processors.	ITC	2007	DBLP DOI BibTeX RDF
1	Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz	Chip Multi-Processor Generator.	DAC	2007	DBLP DOI BibTeX RDF
1	Hiroaki Nishikawa, Hiroshi Tomiyasu, Masanobu Okamoto, Masayoshi Sugiyama, Hiroyuki Uchida, Osamu Mizuno, Hiroshi Ishii, Makoto Iwata	CUE-v3: Data-Driven Chip Multi-Processor for Ad hoc and Ubiquitous Networking Environment.	PDPTA	2007	DBLP BibTeX RDF
1	Satoshi Amamiya, Masaaki Izumi, Takanori Matsuzaki, Ryuzo Hasegawa, Makoto Amamiya	Fuce: the continuation-based multithreading processor.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	continuation-based multithread programming, multithreading, thread-level parallelism, chip multi-processor
1	Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun	A practical FPGA-based framework for novel CMP research.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA-based emulation, transactional memory, chip multi-processor
1	Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose	Evaluating design tradeoffs in on-chip power management for CMPs.	ISLPED	2007	DBLP DOI BibTeX RDF	fetch throttling, dynamic voltage scaling, power-aware, chip multi-processor
1	Fengguang Song, Shirley Moore, Jack Dongarra	L2 Cache Modeling for Scientific Applications on Chip Multi-Processors.	ICPP	2007	DBLP DOI BibTeX RDF	cache performance modeling, architecture, chip multi-processor, multi-threaded programming
1	Guangyu Chen, Feihui Li, Mahmut T. Kandemir	Compiler-directed application mapping for NoC based chip multiprocessors.	LCTES	2007	DBLP DOI BibTeX RDF	compilers, power optimization, Network-on-Chip (NoC), application mapping
1	Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk	Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors.	DAC	2007	DBLP DOI BibTeX RDF
1	Linzhi Ning, Wenbin Yao, Jun Ni, Nianmin Yao	Fault-Tolerance CMP Architecture based on SMT Technology.	IMSCCS	2007	DBLP DOI BibTeX RDF	fault tolerance, CMP, thread, SMT
1	Yan Solihin, Fei Guo, Seongbeom Kim, Fang Liu	Supporting Quality of Service in High-Performance Servers.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Tianzhou Chen, Guobing Chen, Hongjun Dai, Qingsong Shi	A function-based on-chip communication design in the heterogeneous multi-core architecture.	MUE	2007	DBLP DOI BibTeX RDF
1	Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh	Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).	SBAC-PAD	2007	DBLP DOI BibTeX RDF
1	Myungho Lee, Yeonseung Ryu, Sugwon Hong, Chungki Lee	Performance Impact of Resource Conflicts on Chip Multi-processor Servers.	PARA	2006	DBLP DOI BibTeX RDF
1	Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven	Compositional, efficient caches for a chip multi-processor.	DATE	2006	DBLP DOI BibTeX RDF
1	JaeWoong Chung, Chi Cao Minh, Austen McDonald, Travis Skare, Hassan Chafi, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun	Tradeoffs in transactional memory virtualization.	ASPLOS	2006	DBLP DOI BibTeX RDF	OS support, virtualization, transactional memory, chip multi-processor
1	Håkan Zeffer, Zoran Radovic, Martin Karlsson, Erik Hagersten	TMA: a trap-based memory architecture.	ICS	2006	DBLP DOI BibTeX RDF	distributed shared memory (DSM), low complexity server design, node coherence checks, server design, simultaneous multi-threading (SMT), software coherence, trap-based memory architecture (TMA), chip multi processor (CMP)
1	Pengyong Ma, Shuming Chen	MID: a Novel Coherency Protocol in Chip Multiprocessor.	CIT	2006	DBLP DOI BibTeX RDF
1	Saisanthosh Balakrishnan, Gurindar S. Sohi	Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs.	ISCA	2006	DBLP DOI BibTeX RDF
1	Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas	PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection.	MICRO	2006	DBLP DOI BibTeX RDF
1	Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede	Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System.	ICCD	2005	DBLP DOI BibTeX RDF
1	Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh	An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor.	ICAC	2005	DBLP DOI BibTeX RDF	Intrusion-tolerant computing, survivable service, buffer overflow, self-healing, rootkits, chip multi processor
1	Mirko Loghi, Massimo Poncino	Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions.	DATE	2005	DBLP DOI BibTeX RDF
1	Yan Solihin, Fei Guo, Seongbeom Kim	Predicting Cache Space Contention in Utility Computing Servers.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Murali Annavaram, Ed Grochowski, John Paul Shen	Mitigating Amdahl's Law through EPI Throttling.	ISCA	2005	DBLP DOI BibTeX RDF
1	Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha	System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Lukas Ruf, Ralph Keller, Bernhard Plattner	A Scalable High-performance Router Platform Supporting Dynamic Service Extensibility On Network and Host Processors.	ICPS	2004	DBLP DOI BibTeX RDF
1	Mladen Nikitovic, Mats Brorsson	A Multiprogrammed Workload Model for Energy and Performance Estimation of Adaptive Chip-Multiprocessors.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Bart D. Theelen, A. C. Verschueren, V. V. Reyes Suárez, M. P. J. Stevens, A. Nuñez	A scalable single-chip multi-processor architecture with on-chip RTOS kernel.	Journal of Systems Architecture	2003	DBLP DOI BibTeX RDF
1	Chris R. Jesshope	Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines.	ACSAC	2001	DBLP DOI BibTeX RDF
1	Ireneusz Karkowski, Henk Corporaal	Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System Design.	DAC	1998	DBLP DOI BibTeX RDF
1	Ireneusz Karkowski, Henk Corporaal	Exploiting Fine- and Coarse-Grain Parallelism in Embedded Programs.	IEEE PACT	1998	DBLP DOI BibTeX RDF	heterogeneous multi-processors, compilers for parallel systems, high performance embedded system design, application-specific architectures