Search results for "chip multiprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Hyunhee Kim, Jung Ho Ahn, Jihong Kim	Replication-aware leakage management in chip multiprocessors with private L2 cache.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage power management, chip multiprocessors, L2 caches
3	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
3	Jinglei Wang, Dongsheng Wang, Yibo Xue, Haixia Wang	An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
3	Ayse Kivilcim Coskun, Richard D. Strong, Dean M. Tullsen, Tajana Simunic Rosing	Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors.	SIGMETRICS/Performance	2009	DBLP DOI BibTeX RDF	reliability, chip multiprocessors, thermal management, simulation methodology
3	Seung Woo Son, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti	A compiler-directed data prefetching scheme for chip multiprocessors.	PPOPP	2009	DBLP DOI BibTeX RDF	compiler, chip multiprocessors, prefetching, helper thread
3	Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang	Improving support for locality and fine-grain sharing in chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	ARMCO, L1-to-L1 direct access, fine-grain sharing, chip multiprocessors, cache coherence
3	Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee	Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors
3	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
3	Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni	Design Exploration of Optical Interconnection Networks for Chip Multiprocessors.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
3	Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi	Core architecture optimization for heterogeneous chip multiprocessors.	PACT	2006	DBLP DOI BibTeX RDF	computer architecture, multi-core architectures, heterogeneous chip multiprocessors
3	Chris R. Jesshope	muTC - An Intermediate Language for Programming Chip Multiprocessors.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Self-adaptive computing, data-driven com-putation, programming chip multiprocessors, concurrent languages
3	Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk	An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors.	ISCIS	2006	DBLP DOI BibTeX RDF	Reliability, DVS, energy minimization, duplication, heterogeneous chip multiprocessors
3	Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan	Heterogeneous Chip Multiprocessors.	IEEE Computer	2005	DBLP DOI BibTeX RDF	Multicore microprocessors, Multiprocessors, Chip multiprocessors, CMP, Heterogeneity, System architectures, Power-aware computing
3	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin	Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	data compression, chip multiprocessors, optimizing compiler
3	Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir	Optimizing Bus Energy Consumption of On-Chip Multiprocessors Using Frequent Values.	PDP	2004	DBLP DOI BibTeX RDF	On-chip Multiprocessors, Power Optimization, Value Locality
2	Anne Benoit, Paul Renaud-Goud, Yves Robert, Rami G. Melhem	Energy-Aware Mappings of Series-Parallel Workflows onto Chip Multiprocessors.	ICPP	2011	DBLP DOI BibTeX RDF	power consumption minimization, chip multiprocessors, scheduling algorithms, series-parallel graphs
2	Enric Herrero, José González, Ramon Canal	Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.	ISCA	2010	DBLP DOI BibTeX RDF	elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
2	Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson	Energy-efficient redundant execution for chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	redundant execution, microarchitecture, transient faults, permanent faults
2	Abhishek Bhattacharjee, Margaret Martonosi	Inter-core cooperative TLB for chip multiprocessors.	ASPLOS	2010	DBLP DOI BibTeX RDF	parallelism, prefetching, translation lookaside buffer
2	Dai N. Bui, Hiren D. Patel, Edward A. Lee	Deploying Hard Real-Time Control Software on Chip-Multiprocessors.	RTCSA	2010	DBLP DOI BibTeX RDF	Chip-multiprocessors, Real-time software, Discrete-Event
2	Muhammad Yasir Qadri, Klaus D. McDonald-Maier	A Fuzzy Logic Reconfiguration Engine for Symmetric Chip Multiprocessors.	CISIS	2010	DBLP DOI BibTeX RDF	Symmetric Chip multiprocessors, Performance, Fuzzy Logic, Energy, Reconfigurable Hardware
2	Anders P. Ravn, Martin Schoeberl	Cyclic executive for safety-critical Java on chip-multiprocessors.	JTRES	2010	DBLP DOI BibTeX RDF
2	Javier Lira, Carlos Molina, Antonio González	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
2	Eddy Z. Zhang, Yunlian Jiang, Xipeng Shen	Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?	PPOPP	2010	DBLP DOI BibTeX RDF	parallel program optimizations, chip multiprocessors, shared cache, thread scheduling
2	Abhishek Bhattacharjee, Margaret Martonosi	Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors.	ISCA	2009	DBLP DOI BibTeX RDF	intel tbb, thread criticality prediction, parallel processing, caches, dvfs
2	Yefu Wang, Kai Ma, Xiaorui Wang	Temperature-constrained power control for chip multiprocessors with online model estimation.	ISCA	2009	DBLP DOI BibTeX RDF	power management, chip multiprocessor, feedback control
2	Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Cooperative shared resource access control for low-power chip multiprocessors.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
2	Wan-Yu Lee, Iris Hui-Ru Jiang	VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, process variation, monte carlo analysis
2	Yu Zhang, Alex K. Jones	Non-uniform fat-meshes for chip multiprocessors.	IPDPS	2009	DBLP DOI BibTeX RDF
2	Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk	Optimizing shared cache behavior of chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
2	Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang	SHARP control: controlled shared cache management in chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
2	Kai Tian, Yunlian Jiang, Xipeng Shen	A study on optimally co-scheduling jobs of different lengths on chip multiprocessors.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	cache contention, cmp scheduling, perfect matching, a*-search, co-scheduling
2	Ahmed Abousamra, Rami G. Melhem, Daniel Mossé	Minimizing expected energy consumption for streaming applications with linear dependencies on chip multiprocessors.	SIES	2009	DBLP DOI BibTeX RDF
2	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
2	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Dynamic cache clustering for chip multiprocessors.	ICS	2009	DBLP DOI BibTeX RDF	non-uniform cache architecture (nuca), chip multiprocessor (cmp)
2	Martin Schoeberl, Wolfgang Puffitsch, Benedikt Huber	Towards Time-Predictable Data Caches for Chip-Multiprocessors.	SEUS	2009	DBLP DOI BibTeX RDF
2	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
2	Omer Khan, Sandip Kundu	Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.	HiPEAC	2009	DBLP DOI BibTeX RDF	Dynamic Thermal Management (DTM), Virtual Thermal Manager (VTM), Dynamic Voltage and Frequency Scaling (DVFS)
2	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
2	Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng, Mishali Naik, Lixia Zhang, Jason Cong	A scalable micro wireless interconnect structure for CMPs.	MOBICOM	2009	DBLP DOI BibTeX RDF	on-chip wireless interconnection network, chip multiprocessors
2	Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez	Parallel Scalability of Video Decoders.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
2	Jieyi Long, Seda Ogrenci Memik, Gokhan Memik, Rajarshi Mukherjee	Thermal monitoring mechanisms for chip multiprocessors.	TACO	2008	DBLP DOI BibTeX RDF	Thermal sensor allocation, nonuniform and uniform sensor placement
2	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparative evaluation of memory models for chip multiprocessors.	TACO	2008	DBLP DOI BibTeX RDF	streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations
2	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Mahmut T. Kandemir, Feihui Li, Mary Jane Irwin, Seung Woo Son	A novel migration-based NUCA design for chip multiprocessors.	SC	2008	DBLP DOI BibTeX RDF
2	Pablo Abad, Valentin Puente, José-Ángel Gregorio	Reducing the Interconnection Network Cost of Chip Multiprocessors.	NOCS	2008	DBLP DOI BibTeX RDF	Chip Multiprocessors, Deadlock, Router Design
2	Yunlian Jiang, Xipeng Shen, Jie Chen 0010, Rahul Tripathi	Analysis and approximation of optimal co-scheduling on chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	CMP scheduling, cache contention, perfect matching, co-scheduling
2	Noel Eisley, Li-Shiuan Peh, Li Shang	Leveraging on-chip networks for data cache migration in chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	network-driven computing, interconnection network, CMP, chip-multiprocessor, migration
2	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible-core chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	flexible cores, multitask scheduling, multicore architectures
2	Abu Saad Papa, Madhu Mutyam	Power management of variation aware chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	chipmulti-processor, process variation, power-aware, adaptive voltage scaling
2	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
2	Sevin Fide, Stephen Jenks	Architecture optimizations for synchronization and communication on chip multiprocessors.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Ramazan Bitirgen, Engin Ipek, José F. Martínez	Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach.	MICRO	2008	DBLP DOI BibTeX RDF
2	Lars Arge, Michael T. Goodrich, Michael J. Nelson, Nodari Sitchinava	Fundamental parallel algorithms for private-cache chip multiprocessors.	SPAA	2008	DBLP DOI BibTeX RDF	parallel external memory, pem, private-cache cmp
2	Zhiyi Yu, Bevan M. Baas	A low-area interconnect architecture for chip multiprocessors.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Qifei Fan, Ge Zhang, Weiwu Hu	A synchronized variable frequency clock scheme in chip multiprocessors.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Christian Bienia, Sanjeev Kumar, Kai Li	PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors.	IISWC	2008	DBLP DOI BibTeX RDF
2	Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin	Implementation and evaluation of a migration-based NUCA design for chip multiprocessors.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	NUCA, post office placement problem, CMP, data migration
2	Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin	Integrated code and data placement in two-dimensional mesh based chip multiprocessors.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Fredrik Warg, Per Stenström	Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Computer architecture, Chip multiprocessors, Thread-level speculation, Thread-level parallelism, Simultaneous multithreading
2	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Nahalal: Cache Organization for Chip Multiprocessors.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
2	Guilin Chen, Mahmut T. Kandemir	An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors.	T. HiPEAC	2007	DBLP DOI BibTeX RDF
2	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	John Cieslewicz, Kenneth A. Ross, Ioannis Giannakakis	Parallel buffers for chip multiprocessors.	DaMoN	2007	DBLP DOI BibTeX RDF
2	Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg	Strategies for Compiling µ TC to Novel Chip Multiprocessors.	SAMOS	2007	DBLP DOI BibTeX RDF
2	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Adaptive L2 Cache for Chip Multiprocessors.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
2	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparing memory systems for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches
2	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	Core fusion: accommodating software diversity in chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, reconfigurable architectures, software diversity
2	Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen	Carbon: architectural support for fine-grained parallelism on chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	loop and task parallelism, CMP, architectural support
2	Sebastian Herbert, Diana Marculescu	Analysis of dynamic voltage/frequency scaling in chip-multiprocessors.	ISLPED	2007	DBLP DOI BibTeX RDF	chip-multiprocessor, dynamic voltage/frequency scaling
2	Alexandra Fedorova, Margo I. Seltzer, Michael D. Smith	Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler.	PACT	2007	DBLP DOI BibTeX RDF
2	Martin Karlsson, Erik Hagersten	Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution.	IPDPS	2007	DBLP DOI BibTeX RDF
2	Michela Becchi, Mark A. Franklin, Patrick Crowley	Performance/area efficiency in chip multiprocessors with micro-caches.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	networking workload, chip multiprocessor, cache hierarchies
2	Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, Rajaraman Ramanarayanan, Balaji Vaidyanathan	Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Ruibin Xu, Rami G. Melhem, Daniel Mossé	Energy-Aware Scheduling for Streaming Applications on Chip Multiprocessors.	RTSS	2007	DBLP DOI BibTeX RDF
2	Haakon Dybdahl, Per Stenström	An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
2	Alaa R. Alameldeen, David A. Wood	Interactions Between Compression and Prefetching in Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
2	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith	Configurable isolation: building high availability systems with commodity multi-core processors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, high availability, fault isolation
2	Sungjune Youn, Hyunhee Kim, Jihong Kim	A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.	ISLPED	2007	DBLP DOI BibTeX RDF	chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache
2	Jeffery A. Brown, Rakesh Kumar, Dean M. Tullsen	Proximity-aware directory-based coherence for multi-core processor architectures.	SPAA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, coherence
2	Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson	Scheduling threads for constructive cache sharing on CMPs.	SPAA	2007	DBLP DOI BibTeX RDF	constructive cache sharing, parallel depth first, thread granularity, working set profiling, chip multiprocessors, scheduling algorithms, work stealing
2	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith	Isolation in Commodity Multicore Processors.	IEEE Computer	2007	DBLP DOI BibTeX RDF	chip multiprocessors, multicore processors, fault isolation
2	Niti Madan, Rajeev Balasubramonian	Power Efficient Approaches to Redundant Multithreading.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	redundant multi-threading (RMT), dynamic frequency scaling, Reliability, power, soft errors, transient faults, heterogeneous chip multiprocessors
2	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	Efficient Synchronization for Embedded On-Chip Multiprocessors.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Haakon Dybdahl, Per Stenström, Lasse Natvig	A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors.	HiPC	2006	DBLP DOI BibTeX RDF
2	Hou Rui, Longbing Zhang, Weiwu Hu	A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors.	Euro-Par	2006	DBLP DOI BibTeX RDF
2	Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir	Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.	ISCA	2006	DBLP DOI BibTeX RDF
2	Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy	An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Nabil Hasasneh, Ian Bell, Chris R. Jesshope	Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.	ARCS	2006	DBLP DOI BibTeX RDF
2	Raphael Fonte Boa, Alexandre Marques Amaral, Dulcinéia Oliveira da Penha, Carlos Augusto Paiva da Silva Martins, Petr Ekel	Parallel Image Segmentation in Reconfigurable Chip Multiprocessors.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
2	Xudong Shi, Zhen Yang, Jih-Kwon Peir, Lu Peng, Yen-Kuang Chen, V. Lee, B. Liang	Coterminous locality and coterminous group data prefetching on chip-multiprocessors.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Michael R. Marty, Mark D. Hill	Coherence Ordering for Ring-based Chip Multiprocessors.	MICRO	2006	DBLP DOI BibTeX RDF
2	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun	Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.	ICPADS	2006	DBLP DOI BibTeX RDF
2	Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha	SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors.	ICPADS	2006	DBLP DOI BibTeX RDF	SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality
2	Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren	Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors.	ICS	2006	DBLP DOI BibTeX RDF	Gauss-Seidel, temporal blocking, CMP, OpenMP, relaxation, orderings, multigrid, Poisson equation, cache blocking
2	Chao-Chin Wu, Kuan-Chou Lai	A Loop Optimization Technique for Speculative Chip Multiprocessors.	IWNAS	2006	DBLP DOI BibTeX RDF
2	Rana Ejaz Ahmed	Energy-Aware Cache Coherence Protocol for Chip-Multiprocessors.	CCECE	2006	DBLP DOI BibTeX RDF
2	Jian Li, José F. Martínez	Dynamic power-performance adaptation of parallel computation on chip multiprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
2	Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Michael Kozuch, Todd C. Mowry, Radu Teodorescu, Anastassia Ailamaki, Limor Fix, Gregory R. Ganger, Bin Lin, Steven W. Schlosser	Log-based architectures for general-purpose monitoring of deployed code.	ASID	2006	DBLP DOI BibTeX RDF	general-purpose task monitoring, log-based architectures, chip multiprocessors
2	Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson	Parallel depth first vs. work stealing schedulers on CMP architectures.	SPAA	2006	DBLP DOI BibTeX RDF	scheduling, caches, chip multiprocessors