Search results for "chip multiprocessors (CMP)"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Javier Lira, Carlos Molina, Antonio González	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
2	Jinglei Wang, Dongsheng Wang, Yibo Xue, Haixia Wang	An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
1	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das	Coordinated power management of voltage islands in CMPs.	SIGMETRICS	2010	DBLP DOI BibTeX RDF	chip multiprocessors (CMP), control theory, GALs, DVFs
1	Eddy Z. Zhang, Yunlian Jiang, Xipeng Shen	Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?	PPOPP	2010	DBLP DOI BibTeX RDF	parallel program optimizations, chip multiprocessors, shared cache, thread scheduling
1	Yefu Wang, Kai Ma, Xiaorui Wang	Temperature-constrained power control for chip multiprocessors with online model estimation.	ISCA	2009	DBLP DOI BibTeX RDF	power management, chip multiprocessor, feedback control
1	Ahmed Abousamra, Rami G. Melhem, Daniel Mossé	Minimizing expected energy consumption for streaming applications with linear dependencies on chip multiprocessors.	SIES	2009	DBLP DOI BibTeX RDF
1	Zheng Chen, Yin-Liang Zhao, Xiao-Yu Pan, Zhao-Yu Dong, Bing Gao, Zhi-Wen Zhong	An Overview of Prophet.	ICA3PP	2009	DBLP DOI BibTeX RDF	Thread partitioning, Pre-computation slice, Speculative Multithreading Architecture, Thread level parallelism, Speculative multithreading
1	Valentina Salapura	Scaling up next generation supercomputers.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	scalability of systems, chip multiprocessors (cmp), multicore, coherence protocols, blue gene
1	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible-core chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	flexible cores, multitask scheduling, multicore architectures
1	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
1	Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni	Design Exploration of Optical Interconnection Networks for Chip Multiprocessors.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
1	Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, David Brooks	System level analysis of fast, per-core DVFS using on-chip switching regulators.	HPCA	2008	DBLP DOI BibTeX RDF
1	Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai	Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective.	ICCD	2008	DBLP DOI BibTeX RDF
1	Jiaxin Li, Ning Deng, Caixia Liu, Mengxiao Liu, Zuo Wang, Qi Zuo	FG-NC: A Schedule Algorithm of Designing Concurrent Multi-direction Data Switch Structure.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Michele Petracca, Keren Bergman, Luca P. Carloni	Photonic networks-on-chip: Opportunities and challenges.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato	Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF
1	Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero	Nebelung: Execution Environment for Transactional OpenMP.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Compiler, OpenMP, Software Transactional Memory, Runtime system
1	Michela Becchi, Mark A. Franklin, Patrick Crowley	Performance/area efficiency in chip multiprocessors with micro-caches.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	networking workload, chip multiprocessor, cache hierarchies
1	Assaf Shacham, Keren Bergman, Luca P. Carloni	The Case for Low-Power Photonic Networks on Chip.	DAC	2007	DBLP DOI BibTeX RDF
1	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato	A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures.	HPCA	2007	DBLP DOI BibTeX RDF
1	Ronald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David Blaauw, Dennis Sylvester	An Energy Efficient Parallel Architecture Using Near Threshold Operation.	PACT	2007	DBLP DOI BibTeX RDF
1	Alexandra Fedorova, Margo I. Seltzer, Michael D. Smith	Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler.	PACT	2007	DBLP DOI BibTeX RDF
1	Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso	HelperCore_DB: Exploiting Multicore Technology for Databases.	PACT	2007	DBLP DOI BibTeX RDF
1	Assaf Shacham, Keren Bergman, Luca P. Carloni	On the Design of a Photonic Network-on-Chip.	NOCS	2007	DBLP DOI BibTeX RDF
1	Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew Dinn, Chris C. Kirkham, Ian Watson	Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation.	Euro-Par	2007	DBLP DOI BibTeX RDF	Automatic parallelization, dynamic execution, feedback-directed optimization
1	Shuming Chen, Pengyong Ma	FROCM: A Fair and Low-Overhead Method in SMT Processor.	HPCC	2007	DBLP DOI BibTeX RDF
1	Milos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrián Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero	Transactional Memory and OpenMP.	IWOMP	2007	DBLP DOI BibTeX RDF	STM Library, Compiler, OpenMP, Software Transaction Memory
1	Bjørn Jager, Mario Porrmann, Ulrich Rückert	Bio-inspired massively parallel architectures for nanotechnologies.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Xiaoqi Yang, Qilong Zheng, Guoliang Chen, Zhen Yao	Reverse Compilation for Speculative Parallel Threading.	PDCAT	2006	DBLP DOI BibTeX RDF
1	Mario Donato Marino	32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
1	Nabil Hasasneh, Ian Bell, Chris R. Jesshope	Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.	ARCS	2006	DBLP DOI BibTeX RDF
1	Hou Rui, Longbing Zhang, Weiwu Hu	A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors.	Euro-Par	2006	DBLP DOI BibTeX RDF
1	Mario Donato Marino	L2-Cache Hierarchical Organizations for Multi-core Architectures.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
1	Jaydeep Marathe, Frank Mueller, Bronis R. de Supinski	A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks.	ICS	2005	DBLP DOI BibTeX RDF	SMPs, program instrumentation, coherence protocols, hardware performance monitoring, cache analysis, dynamic binary rewriting
1	Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas	Thread-Level Speculation on a CMP can be energy efficient.	ICS	2005	DBLP DOI BibTeX RDF
1	Bjørn Jager, Jörg-Christian Niemann, Ulrich Rückert	Analytical approach to massively parallel architectures for nanotechnologies.	ASAP	2005	DBLP DOI BibTeX RDF
1	Martin Karlsson, Erik Hagersten, Kevin E. Moore, David A. Wood	Exploring Processor Design Options for Java-Based Middleware.	ICPP	2005	DBLP DOI BibTeX RDF	Java, Middleware, CMP, workloads, ILP, Characterization
1	Michael Zhang, Krste Asanovic	Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
1	Partha Kundu, Murali Annavaram, Trung A. Diep, John Paul Shen	A case for shared instruction cache on chip multiprocessors running OLTP.	SIGARCH Computer Architecture News	2004	DBLP DOI BibTeX RDF
1	Ram Rangan, Neil Vachharajani, Manish Vachharajani, David I. August	Decoupled Software Pipelining with the Synchronization Array.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen	Conjoined-Core Chip Multiprocessing.	MICRO	2004	DBLP DOI BibTeX RDF
1	Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir	Optimizing Bus Energy Consumption of On-Chip Multiprocessors Using Frequent Values.	PDP	2004	DBLP DOI BibTeX RDF	On-chip Multiprocessors, Power Optimization, Value Locality