Search results for "chip-multiprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Magnus Jahre, Lasse Natvig	A light-weight fairness mechanism for chip multiprocessor memory systems.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	dynamic miss handling architecture, miss status holding register, fairness, chip multiprocessor, interference, mechanism
3	Xi Zhang, Dongsheng Wang, Yibo Xue, Haixia Wang, Jinglei Wang	A Novel Cache Organization for Tiled Chip Multiprocessor.	APPT	2009	DBLP DOI BibTeX RDF	Multi-level Directory, Chip Multiprocessor(CMP), Cache Organization, Tiled Architecture
3	Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro	FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	Secure mobile terminal, chip multiprocessor, SELinux
3	Sebastian Herbert, Diana Marculescu	Characterizing chip-multiprocessor variability-tolerance.	DAC	2008	DBLP DOI BibTeX RDF	frequency islands, chip-multiprocessor, process variability
3	Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai	Thread Allocation in Chip Multiprocessor Based Multithreaded Network Processors.	AINA	2008	DBLP DOI BibTeX RDF	thread allocation, simulation, modeling, Petri net, chip multiprocessor
3	Michael Gschwind	The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor.	International Journal of Parallel Programming	2007	DBLP DOI BibTeX RDF	compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor
3	Slo-Li Chu	Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture.	EUC	2007	DBLP DOI BibTeX RDF	Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
3	Slo-Li Chu	Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture.	LCPC	2007	DBLP DOI BibTeX RDF	Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
3	Li Yang, Lu Peng	SecCMP: a secure chip-multiprocessor architecture.	ASID	2006	DBLP DOI BibTeX RDF	security, fault-tolerance, encryption, chip-multiprocessor
3	Taeho Kgil, Shaun D'Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Trevor N. Mudge, Steven K. Reinhardt, Krisztián Flautner	PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor.	ASPLOS	2006	DBLP DOI BibTeX RDF	3D stacking technology, tier 1 server, web/file/streaming server, low power, chip multiprocessor, full-system simulation
3	Peter G. Sassone, D. Scott Wills	Scaling Up the Atlas Chip-Multiprocessor.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Dynamic multithreading, chip-multiprocessor, scaling
3	Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro	FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	secure mobile terminal, chip multiprocessor, linux
3	Mladen Nikitovic, Mats Brorsson	An adaptive chip-multiprocessor architecture for future mobile terminals.	CASES	2002	DBLP DOI BibTeX RDF	chip-multiprocessor (CMP), power consumption, mobile terminals, energy-aware scheduling
3	Satoshi Matsushita	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
3	Lucian Codrescu, D. Scott Wills, James D. Meindl	Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Thread speculation, multiscalar, parallelization, chip-multiprocessor, multithreading, value prediction
2	Takeshi Ogasawara	Scalability limitations when running a Java web server on a chip multiprocessor.	SYSTOR	2010	DBLP DOI BibTeX RDF	performance, multi-cores, JVMs, web servers
2	Long Zheng, Mianxiong Dong, Song Guo, Minyi Guo, Li Li	I-Cache Tag Reduction for Low Power Chip Multiprocessor.	ISPA	2009	DBLP DOI BibTeX RDF	tag reduction, chip multiprocessor, energy saving
2	Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi	Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi	Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Martin Schoeberl, Peter P. Puschner, Raimund Kirner	A Single-Path Chip-Multiprocessor System.	SEUS	2009	DBLP DOI BibTeX RDF
2	Mainak Chaudhuri	PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.	HPCA	2009	DBLP DOI BibTeX RDF
2	Wan-Yu Lee, Iris Hui-Ru Jiang	VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, process variation, monte carlo analysis
2	Mainak Chaudhuri	Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.	MICRO	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, replacement policy, last-level cache
2	Degui Feng, Guanjun Jiang, Tiefei Zhang, Wei Hu, Tianzhou Chen, Mingteng Cao	SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework.	APPT	2009	DBLP DOI BibTeX RDF	synchronization, Chip multiprocessor, transactional memory, scratchpad memory
2	Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang	Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003	Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.	PACT	2008	DBLP DOI BibTeX RDF	ia32, on-chip integration, chip multiprocessor, heterogeneous
2	Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz	Verification of chip multiprocessor memory systems using a relaxed scoreboard.	MICRO	2008	DBLP DOI BibTeX RDF
2	Christof Pitter	Time-predictable memory arbitration for a Java chip-multiprocessor.	JTRES	2008	DBLP DOI BibTeX RDF	Java, chip-multiprocessor, shared memory, worst-case execution time
2	Xin Jin, Stephen B. Furber, John V. Woods	Efficient modelling of spiking neural networks on a scalable chip multiprocessor.	IJCNN	2008	DBLP DOI BibTeX RDF
2	Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Rawson III	Scaling and Packing on a Chip Multiprocessor.	IPDPS	2007	DBLP DOI BibTeX RDF
2	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity.	IPDPS	2007	DBLP DOI BibTeX RDF
2	Jugash Chandarlapati, Mainak Chaudhuri	LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation.	ICCD	2007	DBLP DOI BibTeX RDF
2	Philip Machanick	Design principles for a virtual multiprocessor.	SAICSIT Conf.	2007	DBLP DOI BibTeX RDF	chip multiprocessor, instruction-level parallelism
2	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network.	HiPC	2007	DBLP DOI BibTeX RDF	Heterogeneus On-Chip Interconnection Network, Chip-Multiprocessor, Energy-Efficient Architectures, Parallel Scientific Applications
2	Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert	GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications.	ARCS	2006	DBLP DOI BibTeX RDF
2	Raphael Fonte Boa, Dulcinéia Oliveira da Penha, Alexandre Marques Amaral, Márcio Oliveira Soares de Souza, Carlos Augusto Paiva da Silva Martins, Petr Yakovlevitch Ekel	RCMP: A Reconfigurable Chip-Multiprocessor Architecture.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
2	Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou	Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
2	Haixia Wang, Dongsheng Wang, Peng Li	Acceleration Techniques for Chip-Multiprocessor Simulator Debug.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
2	Michela Becchi, Patrick Crowley	Dynamic thread assignment on heterogeneous multiprocessor architectures.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor, heterogeneous architectures
2	Michael Gschwind	Chip multiprocessing and the cell broadband engine.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	compute-transfer parallelism (CTP), cell broadband engine, memory-level parallelism (MLP), chip multiprocessing, heterogeneous chip multiprocessor
2	Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir	Multi-compilation: capturing interactions among concurrently-executing applications.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	multi-compilation, compiler, chip multiprocessor
2	Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha	SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors.	ICPADS	2006	DBLP DOI BibTeX RDF	SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality
2	Pedro Trancoso, Paraskevas Evripidou, Kyriakos Stavrou, Costas Kyriacou	A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model.	International Journal of Parallel Programming	2006	DBLP DOI BibTeX RDF	data-driven execution, parallel processing, Chip multiprocessor, multithreading
2	H. Ando, Nestoras Tzartzanis, William W. Walker	A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso	DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor.	SAMOS	2005	DBLP DOI BibTeX RDF
2	Francisco J. Villa, Manuel E. Acacio, José M. García	Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.	HPCC	2005	DBLP DOI BibTeX RDF
2	Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh	An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor.	ICAC	2005	DBLP DOI BibTeX RDF	Intrusion-tolerant computing, survivable service, buffer overflow, self-healing, rootkits, chip multi processor
2	Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo	An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor.	DATE	2005	DBLP DOI BibTeX RDF
2	Akira Yamawaki, Masahiko Iwane	Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor.	ISPAN	2005	DBLP DOI BibTeX RDF
2	Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA substrate for flexible CMP cache sharing.	ICS	2005	DBLP DOI BibTeX RDF	cache sharing, non-uniform cache architecture, chip-multiprocessor
2	Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Ozcan Ozturk, Mustafa Karaköy, Ugur Sezer	Optimizing Array-Intensive Applications for On-Chip Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	On-chip multiprocessor, adaptive loop parallelization, embedded systems, energy consumption, integer linear programming, constrained optimization
2	Seongbeom Kim, Dhruba Chandra, Yan Solihin	Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture.	IEEE PACT	2004	DBLP DOI BibTeX RDF
2	Wenbin Yao, Dongsheng Wang, Weimin Zheng	A Fault-Tolerant Single-Chip Multiprocessor.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
2	Mohamed M. Zahran	On cache memory hierarchy for Chip-Multiprocessor.	SIGARCH Computer Architecture News	2003	DBLP DOI BibTeX RDF
2	Magnus Ekman, Per Stenström	Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores.	ICPP	2003	DBLP DOI BibTeX RDF
2	Chouki Aktouf	A Complete Strategy for Testing an On-Chip Multiprocessor Architecture.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
2	Shuichi Sakai	CMP on SoC: Architect's View.	ISSS	2002	DBLP DOI BibTeX RDF	CMP (Chip Multiprocessor), I/O centric, SoC (System on Chip), parallel processing, dependability
2	J. Robert Heath, Andrew Tan	Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF	Real-time reconfigurable architecture, analytic functional modeling, real-time testing and functional/performance verification, design, FPGA prototyping
2	Venkata Krishnan, Josep Torrellas	A Chip-Multiprocessor Architecture with Speculative Multithreading.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Chip-multiprocessor, speculative multithreading, data-dependence speculation, control speculation
2	Markus Rudack, Dirk Niggemeyer	Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF
2	Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata	An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.	EUROMICRO	1999	DBLP DOI BibTeX RDF
2	Lucian Codrescu, D. Scott Wills	Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.	ICCD	1999	DBLP DOI BibTeX RDF
2	Venkata Krishnan, Josep Torrellas	The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	register communication, Chip-multiprocessor, speculative multithreading, data-dependence speculation
2	Lance Hammond, Mark Willey, Kunle Olukotun	Data Speculation Support for a Chip Multiprocessor.	ASPLOS	1998	DBLP DOI BibTeX RDF
2	Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Kenneth G. Wilson, Kunyung Chang	The Case for a Single-Chip Multiprocessor.	ASPLOS	1996	DBLP DOI BibTeX RDF
2	Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki	A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor.	HPCA	1996	DBLP DOI BibTeX RDF
1	Hammad Rashid, Clara Novoa, Mark McKenney, Apan Qasem	Efficient parallel solutions to the integral knapsack problem on current chip-multiprocessor systems.	IJPEDS	2012	DBLP DOI BibTeX RDF
1	Matthew DeVuyst, Ashish Venkat, Dean M. Tullsen	Execution migration in a heterogeneous-ISA chip multiprocessor.	ASPLOS	2012	DBLP DOI BibTeX RDF
1	Pablo Prieto, Valentin Puente, José-Ángel Gregorio	Multilevel Cache Modeling for Chip-Multiprocessor Systems.	Computer Architecture Letters	2011	DBLP DOI BibTeX RDF
1	Sanghoon Lee 0006, James Tuck	Automatic parallelization of fine-grained meta-functions on a chip multiprocessor.	CGO	2011	DBLP DOI BibTeX RDF
1	Limin Han, Deyuan Gao, Xiaoya Fan, Liwen Shi, Jianfeng An	Global Prefetcher Aggressiveness Control for Chip-Multiprocessor.	CIS	2011	DBLP DOI BibTeX RDF
1	Mohammad Ghasemazar, Massoud Pedram	Variation aware dynamic power management for chip multiprocessor architectures.	DATE	2011	DBLP BibTeX RDF
1	Fakhar Anjam, Muhammad Nadeem, Stephan Wong	Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor.	DATE	2011	DBLP BibTeX RDF
1	Malèk Channoufi, Pierre Lecoy, Rabah Attia, Bruno Delacressonniere, S. Garcia	Toward All Optical Interconnections in Chip Multiprocessor (2).	ReConFig	2011	DBLP DOI BibTeX RDF
1	Sanghoon Lee 0006, Devesh Tiwari, Yan Solihin, James Tuck	HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor.	HPCA	2011	DBLP DOI BibTeX RDF
1	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen	Optimal memory controller placement for chip multiprocessor.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström	Implications of Merging Phases on Scalability of Multi-core Architectures.	ICPP	2011	DBLP DOI BibTeX RDF	Redcution operations, Chip Multiprocessor, Amdahl's Law
1	Taecheol Oh, Kiyeon Lee, Sangyeun Cho	An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing.	MASCOTS	2011	DBLP DOI BibTeX RDF	simulation, performance modeling, Chip multiprocessor (CMP), resource sharing
1	Omer Khan, Sandip Kundu	Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors.	IEEE Trans. Dependable Sec. Comput.	2011	DBLP DOI BibTeX RDF	hard error detection, isolation and tolerance, Chip Multiprocessor (CMP), hardware/software codesign
1	Xiaorui Wang, Kai Ma, Yefu Wang	Adaptive Power Control with Online Model Estimation for Chip Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	power capping, cache resizing, online model estimation, chip multiprocessor, Power control, feedback control
1	D. Ramakrishnan, Y. L. Wu, W. B. Jone	Design and Analysis of Location Caches in a NoC-Based Chip Multiprocessor System.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Christof Pitter, Martin Schoeberl	A real-time Java chip-multiprocessor.	ACM Trans. Embedded Comput. Syst.	2010	DBLP DOI BibTeX RDF
1	Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer	Quality of service shared cache management in chip multiprocessor architecture.	TACO	2010	DBLP DOI BibTeX RDF
1	Quentin L. Meunier, Frédéric Pétrot, Jean-Louis Roch	Hardware/software support for adaptive work-stealing in on-chip multiprocessor.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Ozcan Ozturk	Improving chip multiprocessor reliability through code replication.	Computers & Electrical Engineering	2010	DBLP DOI BibTeX RDF
1	Long Zheng, Mianxiong Dong, Hai Jin, Minyi Guo, Song Guo, Xuping Tu	The Core Degree Based Tag Reduction on Chip Multiprocessor to Balance Energy Saving and Performance Overhead.	NPC	2010	DBLP DOI BibTeX RDF
1	Shaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu	Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor.	ISQED	2010	DBLP DOI BibTeX RDF
1	Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram	Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint.	ISQED	2010	DBLP DOI BibTeX RDF
1	Christophe Bobda, Philipp Mahr, Benjamin Andres, Harold Ishebabi	Application-driven architecture synthesis of on-chip Multiprocessor systems.	HPCS	2010	DBLP DOI BibTeX RDF
1	David Stevens, Vassilios Chouliaras	LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen	Operating System Processor Scheduler Design for Future Chip Multiprocessor.	ARCS Workshops	2010	DBLP BibTeX RDF
1	Kunle Olukotun	Chip multiprocessor architecture: A programmability-driven approach.	IPDPS	2010	DBLP DOI BibTeX RDF
1	Konstantinos Krommydas, George Tsoublekas, Christos D. Antonopoulos, Nikolaos Bellas	Mapping and optimization of the AVS video decoder on a high performance chip multiprocessor.	ICME	2010	DBLP DOI BibTeX RDF
1	Danfeng Zhu, Rui Wang 0014, Hui Wang, Depei Qian, Zhongzhi Luan, Tianshu Chu	A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor.	ICA3PP	2010	DBLP DOI BibTeX RDF
1	Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram	Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Jiayin Li, Meikang Qiu, Jianwei Niu, Tianzhou Chen, Yongxin Zhu	Real-Time Constrained Task Scheduling in 3D Chip Multiprocessor to Reduce Peak Temperature.	EUC	2010	DBLP DOI BibTeX RDF
1	Magnus Jahre, Marius Grannæs, Lasse Natvig	DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Dan Gibson, David A. Wood	Forwardflow: a scalable core for power-constrained CMPs.	ISCA	2010	DBLP DOI BibTeX RDF	scalable core, chip multiprocessor (cmp), power