Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Volkhard Klinger	DiPaCS: a new concept for parallel circuit simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	DiPaCS system, parallel circuit simulation, distributed parallel circuit simulator, integrated circuit simulation, hierarchical circuit simulator, parallel processing, parallel programming, iterative methods, parallel machines, circuit analysis computing, integrated circuit layout, multicomputer systems, parallel iterative method
7	Dominik Stoffel, Wolfgang Kunz	Record & play: a structural fixed point iteration for sequential circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
7	Hideaki Doi, Yoko Suzuki, Yasuhiko Hara, Tadashi Iida, Yasuhiro Fujishita, Koichi Karasaki	Real-Time X-Ray Inspection of 3D Defects in Circuit Board Patterns. (PDF / PS)	ICCV	1995	DBLP DOI BibTeX RDF	printed circuit layout, X-ray applications, real time X-ray inspection, real-time X-ray inspection, 3D defect, 3-D defects, circuit board patterns, three dimensional defects, fine PCB patterns, sphere surface, X-ray detector, defect detection algorithm, heavy shading, real-time systems, feature extraction, feature extraction, signal processing, inspection, circuit analysis computing, X-ray images, printed circuit board, printed circuit testing, perspective transform, intensity variation, defect detection techniques
6	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	adiabatic logic circuit, power supply circuit, CMOS, dynamic circuit, low power circuit
6	Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia Sanda	Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	imaging circuit analysis, IBM G6 microprocessor, non-invasive backside timing, Picosecond Imaging Circuit Analysis, waveform extraction, integrated circuit testing, timing analysis, race condition, circuit switching, integrated memory circuits, hazards and race conditions, L1 cache
6	Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer	On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient
6	Fabian Vargas, Alexandre M. Amory	Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transient-fault tolerant VHDL descriptions, area overhead analysis, reliable complex circuit design, harmful environments, reliability level, early-estimation, maximum area overhead, redundancy insertion, application minimum reliability requirement, FT-PRO tool, fault tolerant computing, redundancy, microprocessor, integrated circuit design, circuit CAD, CAD tool, transients, reliability estimation, memory elements, integrated circuit reliability, fault-tolerant circuit
6	S. K. Gupta, M. M. Hasan	KANSYS: a CAD tool for analog circuit synthesis.	VLSI Design	1996	DBLP DOI BibTeX RDF	KANSYS, analog circuit synthesis, knowledge intensive hierarchical design, transistor circuit designs, functional circuits, knowledge based systems, hierarchy, integrated circuit design, circuit CAD, CAD tool, analogue integrated circuits, design knowledge, process specifications
6	Narayanan Vijaykrishnan, N. Ranganathan	SUBGEN: a genetic approach for subcircuit extraction.	VLSI Design	1996	DBLP DOI BibTeX RDF	SUBGEN model, subcircuit extraction, large circuit graph, genetic algorithms, genetic algorithm, graph theory, computer-aided design, integrated circuit design, circuit CAD, CMOS integrated circuits, CMOS circuit, integrated circuit modelling
6	Eric Felt, Alberto L. Sangiovanni-Vincentelli	Optimization of analog IC test structures.	VTS	1996	DBLP DOI BibTeX RDF	integrated circuit measurement, analog IC test structures, circuit parameters, statistical analysis, integrated circuit testing, accuracy, circuit optimisation, design of experiments, design of experiments, analogue integrated circuits, statistical techniques, network parameters, integrated circuit noise, measurement noise
6	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
6	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
5	Kai Strunz, Qianli Su	Stochastic formulation of SPICE-type electronic circuit simulation with polynomial chaos.	ACM Trans. Model. Comput. Simul.	2008	DBLP DOI BibTeX RDF	Galerkin projection, electronic circuit, nonsampling stochastic analysis, tolerance analysis, SPICE, circuit simulation, spectral methods, transients, power electronics, stochastic differential equations, polynomial chaos, Circuit modeling
5	Paul Tarau, Brenda Luderman	Revisiting exact combinational circuit synthesis.	SAC	2008	DBLP DOI BibTeX RDF	exact combinational circuit synthesis, logic programming and circuit design, minimal transistor-count circuit synthesis
5	Paul Tarau, Brenda Luderman	A Logic Programming Framework for Combinational Circuit Synthesis.	ICLP	2007	DBLP DOI BibTeX RDF	logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis
5	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
5	Abby A. Ilumoka	Efficient prediction of interconnect crosstalk using neural networks.	ICTAI	2000	DBLP DOI BibTeX RDF	interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration
5	Lluis Ribas, Jordi Carrabina	Digital MOS Circuit Partitioning with Symbolic Modeling.	DATE	1999	DBLP DOI BibTeX RDF	switch-level circuit analysis, symbolic circuit traversal, circuit partitioning, symbolic modeling
5	Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu	Circuit optimization via adjoint Lagrangians.	ICCAD	1997	DBLP DOI BibTeX RDF	Adjoint circuit, Optimization, Circuit simulation, Trust region, Augmented Lagrangian, Circuit tuning
5	Sumit Roy, Prithviraj Banerjee	A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	algebraic factorization, circuit replication, totally independent factorization, L-shaped partitioning strategy, rectangle interaction, ex1010 circuit, sequential kernel extraction algorithms, SIS sequential circuit synthesis system, quality degradation, parallel algorithms, logic synthesis, logic CAD, circuit partitions, divide-and-conquer strategy
5	F. Mohamed, M. Manzouki, Anton Biasizzo, Franc Novak	Analog circuit simulation and troubleshooting with FLAMES.	VTS	1996	DBLP DOI BibTeX RDF	analog circuit simulation, model-based expert system, VLSI, fuzzy logic, fuzzy logic, integrated circuit testing, circuit analysis computing, analogue integrated circuits, troubleshooting, FLAMES, diagnostic expert systems
5	Ayman I. Kayssi	Macromodeling C- and RC-loaded CMOS inverters for timing analysis.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling
5	Carlton Bickford, Marie S. Teo, Gary Wallace, John A. Stankovic, Krithi Ramamritham	A robotic assembly application on the Spring real-time system. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	printed circuit manufacture, printed circuit layout, robotic assembly application, Spring real-time system, run-time system support, predictability demands, robotic work-cell, circuit board assembly, user understanding, target hardware properties, process layout, resource layout, shared resource usage, process suspension, efficient run-time representation, real-time systems, robots, timing, completeness, flexibility, reengineering, timing analysis, circuit layout CAD, assembling, systems re-engineering, interprocess communication, program representation, porting, ease of use, industrial robots, software development tools
5	Anantha Chandrakasan	Ultra low power digital signal processing.	VLSI Design	1996	DBLP DOI BibTeX RDF	ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
5	Pradip Mandal, V. Visvanathan	Design of high performance two stage CMOS cascode op-amps with stable biasing.	VLSI Design	1996	DBLP DOI BibTeX RDF	two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability
5	Yinghua Min, Zhuxing Zhao, Zhongcheng Li	Boolean process-an analytical approach to circuit representation (II).	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	waveform analysis, circuit representation, logical behavior, waveform functions, mathematical tools, waveform polynomials, input transitions, VLSI, Boolean functions, timing, design for testability, logic design, logical design, polynomials, integrated circuit design, VLSI circuits, performance enhancement, timing behavior, Boolean process, circuit delay
5	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
5	Imtiaz P. Shaik, Michael L. Bushnell	Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .	VTS	1995	DBLP DOI BibTeX RDF	low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions
5	Jin-Tai Yan, Pei-Yung Hsiao	A new fuzzy-clustering-based approach for two-way circuit partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	fuzzy-clustering-based approach, two-way circuit partitioning, circuit netlist, undirected edge-weighted graph, tree net model, clustering distance, area information, area-balanced constraints, circuit benchmarks, VLSI, simulated annealing, network topology, trees (mathematics), fuzzy set theory, logic partitioning, fuzzy c-means clustering, fuzzy memberships
5	S. C. Prasad, Kaushik Roy	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
5	Jin-Tai Yan	Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	fuzzy neural nets, connection-oriented net model, fuzzy clustering techniques, K-way circuit partitioning, chain net model, cut analysis, multiple-pin net, edge-weighted graph, MCNC circuit benchmarks, partitioning balance, partitioning cut, computational complexity, complexity, fuzzy logic, high level synthesis, circuit analysis computing, hypergraph, fuzzy c-means clustering, mapped graph, fuzzy memberships
5	Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs	Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling
5	Sachin S. Sapatnekar, Weitong Chuang	Power vs. delay in gate sizing: conflicting objectives?	ICCAD	1995	DBLP DOI BibTeX RDF	power-delay tradeoffs, short-circuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power
5	Manoj Franklin	Fast computation of C-MISR signatures.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits
5	L. F. Fuller, C. Kraaijenvanger	Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education
5	J. T. Mowchenko, Y. Yang	Optimizing wiring space in slicing floorplans.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	wiring space optimisation, slicing floorplans, net density, sibling rectangles, circuit modules, routed layouts, VLSI, heuristic, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, branch and bound algorithm, wiring, IC layout
5	Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar	Testability-oriented channel routing.	VLSI Design	1995	DBLP DOI BibTeX RDF	IC testing quality, testability-oriented channel routing, IC layout modification, test escape probability, iterative channel routing tool, fault undetectability, WrenTR, fault diagnosis, integrated circuit testing, design for testability, fault detectability, network routing, circuit layout CAD, bridging fault, circuit optimisation, integrated circuit layout, design strategies, yield loss, integrated circuit yield
5	Trevor J. Smedley	A High-Level Visual Language for the Graphical Description of Digital Circuits. (PDF / PS)	VL	1995	DBLP DOI BibTeX RDF	pulse circuits, high-level visual language, graphical description, programming language systems, digital design systems, full-featured visual programming language, complex circuit specification, repetitive structures, conditional structures, visual languages, circuit analysis computing, circuit CAD, digital circuits, engineering graphics, program structures, digital circuit design
5	Akio Okazaki, Takashi Kondo, Kazuhiro Mori, Shou Tsunekawa, Eiji Kawamoto	An Automatic Circuit Diagram Reader with Loop-Structure-Based Symbol Recognition.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	automatic circuit diagram reader, loop-structure-based symbol recognition, logic circuit diagram reader, symbol segmentation, symbol identification, decision-tree control, character string recognition, connecting line analysis, computer vision, feature extraction, computerised pattern recognition, computerised pattern recognition, logic CAD, template matching, circuit CAD, VLSI-CAD
4	Zhai Zhang, Youren Wang, Shanshan Yang, Rui Yao, Jiang Cui	The research of self-repairing digital circuit based on embryonic cellular array.	Neural Computing and Applications	2008	DBLP DOI BibTeX RDF	Self-repairing digital circuit, Embryonic cellular array, Fault-tolerance design, Digital circuit design
4	Yoichi Sasaki, Kazuteru Namba, Hideo Ito	Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
4	Felipe Machado, Teresa Riesgo, Yago Torroja	Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.	PATMOS	2008	DBLP DOI BibTeX RDF	activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design
4	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
4	Guoyong Shi, Weiwei Chen, C.-J. Richard Shi	A Graph Reduction Approach to Symbolic Circuit Analysis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	symbolic analog circuit simulator, symbolic circuit analysis, recursive sign determination algorithm, binary decision diagram, graph reduction
4	Hai Lin, Yu Wang 0002, Rong Luo, Huazhong Yang, Hui Wang 0004	IR-drop Reduction Through Combinational Circuit Partitioning.	PATMOS	2006	DBLP DOI BibTeX RDF	Static Timing Analysis, IR-drop, circuit partitioning
4	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Modeling and analysis of circuit performance of ballistic CNFET.	DAC	2006	DBLP DOI BibTeX RDF	ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance
4	Hajime Shibata, Adrian Stoica, Nobuo Fujii	Controllable decoding for automated analog circuit structure design.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Automated circuit synthesis, Genetic algorithm, Analog circuit
4	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. (PDF / PS)	ISMVL	2000	DBLP DOI BibTeX RDF	dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
4	Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
4	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
4	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	Testing for the programming circuit of LUT-based FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programming circuit, control circuit, configuration memory cell array, FPGA, fault model, SRAM, shift registers, shift registers, look-up table
4	Andy Negoi, Alain Guyot, Jacques Zimmermann	A dedicated circuit for charged particles simulation using the Monte Carlo method.	ASAP	1997	DBLP DOI BibTeX RDF	dedicated circuit, charged particles simulation, dedicated integrated circuit, integro-differential Boltzmann equation, direct statistical computation, simulated particles distribution function, semiconductor device hardware simulator, microdynamical transport, Boltzmann equation, binary format, drift velocity, static uniform electric field, hot carrier effects, computational complexity, Monte Carlo method
4	Anirudh Devgan	Efficient coupled noise estimation for on-chip interconnects.	ICCAD	1997	DBLP DOI BibTeX RDF	coupled noise estimation, dynamic logic circuit families, noise criticality pruning, physical design based noise avoidance, circuit simulation, on-chip interconnects, Elmore delay, noise analysis, timing simulation, integrated circuit noise, deep submicron design
4	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw	Library-less synthesis for static CMOS combinational logic circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance
4	Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault	Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	defect-tolerant circuit, contamination, wafer test, silicon chip, reconfiguration, redundancy, integrated circuit testing, manufacturing, yield, cost model, integrated circuit, figure of merit, fault tolerant circuit
4	Minesh B. Amin, Bapiraju Vinnakota	ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator.	VTS	1996	DBLP DOI BibTeX RDF	ZAMBEZI, parallel pattern simulator, parallel fault simulation, sequential circuit fault simulator, multiple faults simulation, multiple vectors, parallel algorithms, VLSI, fault diagnosis, logic testing, sequential circuits, circuit analysis computing, integrated logic circuits
4	Naim Ben Hamida, Bechir Ayari, Bozena Kaminska	Testing of embedded A/D converters in mixed-signal circuit. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	embedded A/D converters testing, integral nonlinearity error, differential nonlinearity error, offset error, gain error, boolean function manipulation, FFT, histogram, functional testing, transfer function, digital circuit, signal-to-noise ratio, mixed-signal circuit, analogue-digital conversion
4	Vamsi Boppana, W. Kent Fuchs	Integrated fault diagnosis targeting reduced simulation.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS 85 circuit, ISCAS 89 circuit, dynamic techniques, integrated fault diagnosis, precomputed information, reduced simulation, run-time cost reduction, static techniques, combinational circuit, circuit analysis computing, run-time analysis
4	Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet	A symbolic simulation approach in resolving signals' correlation.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools
4	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
4	Sunil R. Das, N. Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
4	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
4	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Segment delay faults: a new fault model.	VTS	1996	DBLP DOI BibTeX RDF	segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects
4	Haluk Konuk, F. Joel Ferguson	An unexpected factor in testing for CMOS opens: the die surface.	VTS	1996	DBLP DOI BibTeX RDF	surface phenomena, electric charge, CMOS opens, die surface, RC interconnect, HSPICE simulations, trapped charge, floating gates, VLSI, integrated circuit testing, CMOS integrated circuits, integrated circuit modelling, circuit model
4	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
4	John W. Sheppard, William R. Simpson	Improving the accuracy of diagnostics provided by fault dictionaries.	VTS	1996	DBLP DOI BibTeX RDF	diagnostics accuracy improvement, digital circuit diagnosis, information flow model, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, circuit analysis computing, digital integrated circuits, fault dictionaries, nearest neighbor classification
4	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
4	Fadi Y. Busaba, Parag K. Lala	A graph coloring based approach for self-checking logic circuit design.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	logic circuit design, bidirectional error, residue weights assignments, output lines, errors identification, graph theory, logic testing, integrated circuit testing, logic design, error detection, error detection, automatic testing, graph coloring, fault location, integrated logic circuits, graph colouring, self-checking, residue codes, single stuck-at fault
4	Wilbert H. F. J. Körver	A universal formalization of the effects of threshold voltages for discrete switch-level circuit models.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits
4	I. S. Abu-Khater, A. Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan	Circuit/architecture for low-power high-performance 32-bit adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit
4	Chantal Ykman-Couvreur, Bill Lin	Optimised state assignment for asynchronous circuit synthesis.	ASYNC	1995	DBLP DOI BibTeX RDF	optimised state assignment, asynchronous circuit synthesis, complete state coding, state graph level, asynchronous benchmarks, circuit area, logic design, encoding, asynchronous circuits, computation time, state assignment
4	Hao Tang, Hung Chang Lin	A Fuzzy Membership Function Circuit Using Hysteretic Resonant Tunneling Diodes. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	switched capacitor networks, signal sampling, fuzzy membership function circuit, hysteretic resonant tunneling diodes, fuzzy logic hardware, hysteretic effect, input sampling, sampled input, intrinsic I-V characteristics, fuzzy logic, integrated logic circuits, membership function, hysteresis, resonant tunnelling diodes, resonant tunneling diodes, circuit performance
4	Goutam Debnath, K. Debnath, R. Fernando	The Pentium processor-90/100, microarchitecture and low power circuit design.	VLSI Design	1995	DBLP DOI BibTeX RDF	BIMOS integrated circuits, Pentium processor-90/100, low power circuit design, BiNMOS process, power consumption reduction, symmetric dual processing feature, multithreaded operating systems, 0.6 micron, 3.3 V, computer architecture, microarchitecture, integrated circuit design, microprocessor chips, 100 MHz
4	Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata	O(n)-depth circuit algorithm for modular exponentiation.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	O(n)-depth circuit algorithm, polynomial-size combinational circuit algorithm, n-bit modular exponentiation, n-bit binary integers, square-and-multiply method, public key cryptography, combinational circuits, digital arithmetic, modular exponentiation
4	Mike Chou, Jacob K. White	Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect.	ICCAD	1995	DBLP DOI BibTeX RDF	Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics)
4	Amir H. Farrahi, Majid Sarrafzadeh	System partitioning to maximize sleep time.	ICCAD	1995	DBLP DOI BibTeX RDF	Geo-Part, exploitable sleep time, geometric partitioning heuristic, low-power synthesis, memory refresh circuitry, segment tree data structure, VLSI, logic CAD, integrated circuit design, circuit CAD, circuit optimisation, logic partitioning, partitioning problem, system partitioning
4	Haifang Liao, Wayne Wei-Ming Dai	Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels.	ICCAD	1995	DBLP DOI BibTeX RDF	circuit reduction, scattering parameter, interconnect network, macromodel, Circuit partitioning, circuit synthesis
4	Sudhir K. Jhajharia, Hua Swee Wang	Training diploma students on ATE-related module.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electronic equipment testing, tertiary institution, ATE-related module, diploma students, final year students, Microelectronics option, Electronics and Communication Engineering Department, Singapore Polytechnic, Singapore Polytechnic Education Model, automated test equipment, Advanced Diploma, practical training, laboratory session, training, integrated circuit testing, assessment, teaching, teaching, automatic testing, automatic test equipment, test patterns, printed circuit boards, educational courses, printed circuit testing, industry-standard, electronic engineering education
4	Pierre Fraigniaud, Joseph G. Peters	Structured communication in torus networks.	HICSS	1995	DBLP DOI BibTeX RDF	combinational switching, structured communication, one-to-all data movement patterns, all-to-all data movement patterns, 2D tori, multi-dimensional tori, synchronous circuit-switched routing, multi-scattering, circuit-switching algorithms, short routing, broadcasting, broadcasting, multiprocessor interconnection networks, gossiping, distributed memory systems, network routing, virtual channels, cycles, circuit switching, switching theory, scattering, torus networks, message length, store-and-forward routing
4	K. Y. Wu, P. K. H. Ng, Xing Dong Jia, Richard M. M. Chen, A. M. Layfield	Performance tuning of a multiprocessor sparse matrix equation solver.	HICSS	1995	DBLP DOI BibTeX RDF	multiprocessor sparse matrix equation solver, sparse matrix equation, linear simultaneous equations, electrical circuit, multiprocessor implementation, parallel direct method, parallel algorithms, circuit analysis computing, SPICE, SPICE, circuit simulation, sparse matrices, performance tuning
4	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
4	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
4	Chunduri Rama Mohan, Partha Pratim Chakrabarti	Combined optimization of area and testability during state assignment of PLA-based FSM's.	VLSI Design	1995	DBLP DOI BibTeX RDF	combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
4	Sven Simon, Ralf Bucher, Josef A. Nossek	Retiming of synchronous circuits with variable topology.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits
4	Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana	CODAC-a characterization system for digital and analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	CODAC, characterization system, electrical simulator, procedural interface, customized analysis functions, parallel processing, circuit analysis computing, Monte Carlo methods, circuit CAD, SPICE, SPICE, analog circuits, digital circuits, CAD tool, digital integrated circuits, analogue integrated circuits, circuit analysis, Monte Carlo analysis
4	Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò	Reliability evaluation of combinational logic circuits by symbolic simulation.	VTS	1995	DBLP DOI BibTeX RDF	mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
4	Takushi Tanaka	Parsing Electronic Circuits in a Logic Grammar.	IEEE Trans. Knowl. Data Eng.	1993	DBLP DOI BibTeX RDF	trouble shooting, automatic circuit understanding, circuit structures, definite clause set grammar, DCSG top-down parsing mechanism, trees (mathematics), circuit analysis computing, grammars, structural analysis, formal logic, hierarchical structures, circuit design, words, parse trees, functional blocks, causal analysis, sentence, logic grammar
4	Rohit Kapur, M. Ray Mercer	Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	bounding algorithm, circuit faults, conditional syndromes, auxiliary gate, pseudorandom pattern resistant faults, circuit structure, computational complexity, lower bounds, built-in self test, integrated circuit testing, circuit analysis computing, signal probabilities, testability measurement, random pattern testability
4	Wolfgang Borutzky	Combining Behavioral Block Diagram Modelling with Circuit Simulation.	EUROCAST	1989	DBLP DOI BibTeX RDF	mixed behavioral, circuit-level modelling, electrical macromodels, continuous system simulation, electronic control systems, circuit simulation, functional simulation, block diagrams, signal processing systems
4	Qin-Zhong Ye, Per-Erik Danielsson	Inspection of Printed Circuit Boards by Connectivity Preserving Shrinking.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	PCB manufacture, connectivity preserving shrinking, edge irregularities, printed circuit manufacture, computer vision, computer vision, computerised pattern recognition, computerised pattern recognition, inspection, sensitivity, quality control, quality control, visual inspection, printed circuit boards, pipelined structure
4	Yasuhiko Hara, Hideaki Doi, Koichi Karasaki, Tadashi Iida	A System for PCB Automated Inspection Using Fluorescent Light.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	violet illumination, PCB automated inspection, fluorescent light, nicks, printed circuit board pattern, ultraviolet rays, glass-epoxy, glass-polyimide, high-sensitivity TV camera, silhouette image, fluorescence, pattern recognition, computer vision, computer vision, fault detection, computerised pattern recognition, inspection, circuit analysis computing, fault location, cuts, printed circuit testing, optical fiber, short-circuits
4	D. B. Shu, C. C. Li, J. F. Mancuso, Y. N. Sun	A Line Extraction Method for Automated SEM Inspection of VLSI Resist.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	line extraction method, automated SEM inspection, VLSI resist, precision digital edge-line-detection method, edge contours, submicrometer width, integrated circuit fabrication, computer vision, VLSI, transforms, integrated circuit testing, computerised picture processing, automatic testing, Hough transform, inspection, circuit analysis computing, scanning electron microscopy, scanning electron microscopy
4	Stanley Lass	Automated printed circuit routing with a stepping aperture.	Commun. ACM	1969	DBLP DOI BibTeX RDF	circuit board, printed circuit, stepping aperture, routing, interconnections, lines, computer program, vias, pins, aperture
3	Abdulhadi Shoufan, Zheng Lu, Guido Rößling	A platform for visualizing digital circuit synthesis with VHDL.	ITiCSE	2010	DBLP DOI BibTeX RDF	digital circuit synthesis, visualization, animation, VHDL
3	Jun Liu, Ming-xin Yang, Jian-Bo Wang	Thick Film Integrated Circuit Design of Multi-measurement Module.	APWCS	2010	DBLP DOI BibTeX RDF	Thick film integrated circuit, Signal adjustment circuit, Thermocouple, Spi, Calibration
3	Huang Yushui, Zhu Ling, Xin Yugang	Analysis and Optimization Design of M57959L Module-Based IGBT Drive Circuit.	APWCS	2010	DBLP DOI BibTeX RDF	IGBT, drive circuit, M57959L, optimization circuit, High reliability
3	Ramamohan Paturi, Pavel Pudlák	On the complexity of circuit satisfiability.	STOC	2010	DBLP DOI BibTeX RDF	NP-completeness, circuit satisfiability
3	Jernej Olensek, Árpád Bürmen, Janez Puhan, Tadej Tuma	DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing.	J. Global Optimization	2009	DBLP DOI BibTeX RDF	Analog integrated circuit sizing, Optimization, Simulated annealing, Differential evolution
3	Andrew Zalesky	To burst or circuit switch?	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	all-optical switching, optical circuit switching, path decomposition, stochastic performance modeling, vacation queue, blocking probability, optical burst switching
3	Michal Koucký	Circuit Complexity of Regular Languages.	Theory Comput. Syst.	2009	DBLP DOI BibTeX RDF	Circuit complexity, Regular languages, Upper and lower bounds