Search results for "circuit CAD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	A study of composition schemes for mixed apply/compose based construction of ROBDDs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed apply/compose based construction, ROBDD, reduced ordered binary decision diagram, time-memory tradeoff, graph theory, composition, decomposition, heuristic algorithm, circuit CAD, circuit CAD, network synthesis, top down method, bottom up method
1	Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov	Circuit CAD Tools as a Security Threat.	HOST	2008	DBLP DOI BibTeX RDF
1	Lukasz Zielinski, Bartlomiej Puchalski, Jerzy Rutkowski	Yield enhancement by means of evolutionary computation techniques.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
1	Fabian Vargas, Alexandre M. Amory	Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transient-fault tolerant VHDL descriptions, area overhead analysis, reliable complex circuit design, harmful environments, reliability level, early-estimation, maximum area overhead, redundancy insertion, application minimum reliability requirement, FT-PRO tool, fault tolerant computing, redundancy, microprocessor, integrated circuit design, circuit CAD, CAD tool, transients, reliability estimation, memory elements, integrated circuit reliability, fault-tolerant circuit
1	Abby A. Ilumoka	Efficient prediction of interconnect crosstalk using neural networks.	ICTAI	2000	DBLP DOI BibTeX RDF	interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration
1	Massimo De Santo, Nicola Femia, Giovanni Spagnuolo, F. Arcelli	A novel software architecture for computer-aided analysis of circuits with uncertain parameters.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	ICCAD	1997	DBLP DOI BibTeX RDF	Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations
1	Sharad Kapur, David E. Long	IES3: a fast integral equation solver for efficient 3-dimensional extraction.	ICCAD	1997	DBLP DOI BibTeX RDF	3-dimensional extraction, IES/sup 3/, arbitrary kernels, integral equation solver, integrated circuit structures, circuit CAD
1	Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel	Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation.	Workshop on Parallel and Distributed Simulation	1997	DBLP DOI BibTeX RDF	asynchronous parallel algorithms, dynamic characteristics, redundant work, sequential VLSI circuits, synchronous two stage approach, test set partitioned fault simulation, MPI, Message Passing Interface, shared memory multiprocessor, circuit analysis computing, circuit CAD, software portability
1	Amir A. Khwaja	Enhancing extensibility of the design rule checker of an EDA tool by object-oriented modeling. (PDF / PS)	COMPSAC	1997	DBLP DOI BibTeX RDF	design rule checker, design rule checking systems, electronic design automation tools, semiconductor technology, DRC systems, DRC module, IC package design tool, object oriented modeling technique, abstraction, inheritance, extensibility, object oriented modeling, encapsulation, circuit CAD, dynamic binding, EDA tool
1	Jason Cong, Lei He	An efficient approach to simultaneous transistor and interconnect sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	CH-posynomial programs, STIS, driver/buffer, transistor and interconnect sizing, wire sizing problem, circuit CAD, transistor sizing
1	Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet	A symbolic simulation approach in resolving signals' correlation.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools
1	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
1	S. K. Gupta, M. M. Hasan	KANSYS: a CAD tool for analog circuit synthesis.	VLSI Design	1996	DBLP DOI BibTeX RDF	KANSYS, analog circuit synthesis, knowledge intensive hierarchical design, transistor circuit designs, functional circuits, knowledge based systems, hierarchy, integrated circuit design, circuit CAD, CAD tool, analogue integrated circuits, design knowledge, process specifications
1	Jaswinder Pal Singh, A. Kumar, Sanjeev Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
1	Narayanan Vijaykrishnan, N. Ranganathan	SUBGEN: a genetic approach for subcircuit extraction.	VLSI Design	1996	DBLP DOI BibTeX RDF	SUBGEN model, subcircuit extraction, large circuit graph, genetic algorithms, genetic algorithm, graph theory, computer-aided design, integrated circuit design, circuit CAD, CMOS integrated circuits, CMOS circuit, integrated circuit modelling
1	M. Miegler, Werner Wolz	Development of test programs in a virtual test environment.	VTS	1996	DBLP DOI BibTeX RDF	test programs development, virtual test environment, quality-assured mixed-signal test programs, standard test description language, VTML, Virtual Test Modelling Language, standardized description models, test system resources, equivalent simulation models, VLSI, integrated circuit testing, design for testability, integrated circuit design, circuit CAD, automatic test software
1	Masaru Sanada	A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq.	VTS	1996	DBLP DOI BibTeX RDF	CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration
1	Amir H. Farrahi, Majid Sarrafzadeh	System partitioning to maximize sleep time.	ICCAD	1995	DBLP DOI BibTeX RDF	Geo-Part, exploitable sleep time, geometric partitioning heuristic, low-power synthesis, memory refresh circuitry, segment tree data structure, VLSI, logic CAD, integrated circuit design, circuit CAD, circuit optimisation, logic partitioning, partitioning problem, system partitioning
1	Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe	A delay model for logic synthesis of continuously-sized networks.	ICCAD	1995	DBLP DOI BibTeX RDF	algebraic factorings, computational simplicity, continuous device sizing, continuously-sized networks, electrical noise, library cell, mapped network, logic design, logic synthesis, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, delay model, power constraints
1	Sasan Iman, Massoud Pedram	Two-level logic minimization for low power.	ICCAD	1995	DBLP DOI BibTeX RDF	Power Prime Implicants, low power two-level logic minimization, minimum covering problem, minimum power solution, static CMOS circuits, logic design, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, circuit optimisation, minimisation of switching nets
1	Balakrishnan Iyer, Ramesh Karri, Israel Koren	Phantom redundancy: a high-level synthesis approach for manufacturability.	ICCAD	1995	DBLP DOI BibTeX RDF	fabrication-time reconfigurability, functional unit failure, microarchitecture synthesis, phantom redundancy, genetic algorithm, high level synthesis, high-level synthesis, redundancy, logic design, reconfigurable architectures, manufacturability, microarchitecture, circuit CAD
1	Paul E. R. Lippens, Vijay Nagasamy, Wayne Wolf	CAD challenges in multimedia computing.	ICCAD	1995	DBLP DOI BibTeX RDF	CAD challenges, VLSI systems-on-chips, advanced CAD synthesis tools, high computation rates, high-volume chip, multimedia computer design, multirate computing problem, VLSI, circuit CAD, multimedia computing, memory bandwidth
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Synthesis of multiplier-less FIR filters with minimum number of additions.	ICCAD	1995	DBLP DOI BibTeX RDF	MCM based structures, iterative elimination, low pass FIR filters, circuit CAD, FIR filters, network synthesis, optimizing transformations, binary representations
1	Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi	Design-for-debugging of application specific designs.	ICCAD	1995	DBLP DOI BibTeX RDF	debugging requirements, scheduling, computational complexity, combinatorial optimization, controllability, high level synthesis, design for testability, observability, application specific integrated circuits, circuit CAD, hardware support, polynomial time complexity, Design-for-Debugging, synthesis algorithm
1	Miodrag Potkonjak, Wayne Wolf	Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques.	ICCAD	1995	DBLP DOI BibTeX RDF	allocation algorithms, behavioral synthesis techniques, datapath synthesis criteria, multiple computational tasks, multiple-task examples, periodic hard-real time systems, real-time systems, high level synthesis, logic design, application specific integrated circuits, circuit CAD, circuit optimisation, cost optimization, rate-monotonic scheduling, task sharing, synthesis algorithm, ASIC implementation
1	Sachin S. Sapatnekar, Weitong Chuang	Power vs. delay in gate sizing: conflicting objectives?	ICCAD	1995	DBLP DOI BibTeX RDF	power-delay tradeoffs, short-circuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power
1	Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn	Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.	ICCAD	1995	DBLP DOI BibTeX RDF	acyclic pipelines, area-delay tradeoff, clock skew optimization, cycle-borrowing, logic design, combinational circuits, logic CAD, pipeline processing, circuit CAD, circuit optimisation, gate sizing, logic gates, pipelined circuits, timing specifications
1	Hirendu Vaishnav, Massoud Pedram	Delay optimal partitioning targeting low power VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	clustering, VLSI, partitioning, logic CAD, circuit CAD, integrated logic circuits, power dissipation, VLSI circuits, logic partitioning, delay optimal
1	Jörg Henkel, Rolf Ernst	A path-based technique for estimating hardware runtime in HW/SW-cosynthesis.	ISSS	1995	DBLP DOI BibTeX RDF	hardware runtime, hardware software cosynthesis, local estimation techniques, local list scheduling, path-based technique, scheduling, computational complexity, computer architecture, quality, systems analysis, circuit CAD, computation time, optimising compilers, synthesis tools
1	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
1	Matthew F. Parkinson, Sri Parameswaran	Profiling in the ASP codesign environment.	ISSS	1995	DBLP DOI BibTeX RDF	Automated Synthesis and Partitioning system, Hardware/Software Codesign project, codesign environment, hardware/software codesign methodology, high-level profiling tools, virtual machines, software tools, C, computer architecture, profiling, systems analysis, circuit CAD, workstation, ASP, C code, dedicated hardware, execution profiling
1	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
1	X. Cai, Keith Nabors, Jacob White	Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics.	ARVLSI	1995	DBLP DOI BibTeX RDF	piecewise constant techniques, permittivity, Galerkin techniques, multipole-accelerated capacitance extraction, multiple dielectrics, arbitrary piecewise-constant dielectric medium, IC interconnections, VLSI, VLSI, integrated circuit design, circuit CAD, boundary-elements methods, boundary element method, capacitance, integrated circuit interconnections, Galerkin method, capacitance extraction, 3D structures
1	Scott Hauck, Gaetano Borriello	An evaluation of bipartitioning techniques.	ARVLSI	1995	DBLP DOI BibTeX RDF	bipartitioning techniques, VLSI, logic CAD, integrated circuit design, circuit CAD, logic partitioning, logic partitioning, VLSI CAD
1	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
1	Huy Nguyen, Abhijit Chatterjee	OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions.	ARVLSI	1995	DBLP DOI BibTeX RDF	linear network synthesis, OPTIMUS program, linear circuits, shift-and-add decomposition, behavioral synthesis tool, architectural transformations, numerical matrix transformation algorithms, number-splitting transformation, optimization, high level synthesis, multiplications, circuit CAD, circuit optimisation, matrix decomposition
1	Rong Lin, Stephan Olariu	A simple array processor for binary prefix sums.	ASAP	1995	DBLP DOI BibTeX RDF	binary prefix sums, storage compaction, routing, computational complexity, parallel processing, VLSI, network routing, circuit CAD, array processor, binary sequence, special-purpose architecture, processor assignment, operating system design
1	Doran Wilde, Sanjay V. Rajopadhye	The naive execution of affine recurrence equations.	ASAP	1995	DBLP DOI BibTeX RDF	algorithmic languages, regular arrays, ALPHA language, computer aided design methodology, regular array architectures, algorithmic specification, imperative sequential language C, applicative caching, 1-dimensional storage, formal specification, circuit CAD, hardware description languages, nested loops, polyhedron, transformational approach, C-code, affine recurrence equations
1	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
1	Wallace B. Leigh	A personal computer based VLSI design curriculum.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	VLSI design curriculum, teaching institutions, capstone VLSI course, analog design course, digital design synthesis course, teaching curriculum, VLSI, design methodology, integrated circuit design, circuit CAD, personal computers, computer aided instruction, microcomputer applications, electronic engineering education
1	Enric Pastor, Jordi Cortadella, Oriol Roig	A new look at the conditions for the synthesis of speed-independent circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits
1	Nestoras Tzartzanis, William C. Athas	Design and analysis of a low-power energy-recovery adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
1	James M. Varanelli, James P. Cohoon	A two-stage simulated annealing methodology.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	two-stage simulated annealing methodology, starting temperature determination, problem suite, VLSI, VLSI, formal method, simulated annealing, CAD, integrated circuit design, circuit CAD, optimization problems, circuit optimisation, running time, adaptive schedules, stop criterion
1	M. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward	Using EDIF for software generation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	EDIF, parallel microprocessors, codesign methods, hardware development tools, real-time parallel C code, FPGA, parallel programming, simulated annealing, simulated annealing, software tools, software tool, logic CAD, circuit CAD, C language, scheduling theory, software generation, development systems
1	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
1	Ireneusz Karkowski	Architectural synthesis with possibilistic programming.	HICSS	1995	DBLP DOI BibTeX RDF	possibilistic programming, fuzzy mathematical programming, simultaneous scheduling, FOAS, computational complexity, computational complexity, fuzzy logic, high level synthesis, high-level synthesis, circuit CAD, mathematical programming, possibility theory
1	Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao	Multi-dimensional interleaving for time-and-memory design optimization. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	multidimensional interleaving, time-and-memory design optimization, recursive time-critical sections, multi-dimensional problems, image processing, image processing, optimisation, application specific integrated circuits, application specific integrated circuits, circuit CAD, digital filters, digital filters, optimization technique, iteration space
1	Robert Spence, Lisa Tweedie, Huw Dawkes, Hua Su	Visualization for functional design.	INFOVIS	1995	DBLP DOI BibTeX RDF	visualisation tools, Influence Explorer, Prosection Matrix, engineering artifact design, electronic circuit design, user interfaces, CAD, optimisation, interactive systems, data visualisation, circuit CAD, interactive display, manufacturing process, engineering graphics, functional design
1	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
1	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
1	Raj S. Mitra, Partha S. Roop, Anupam Basu	Implementation of design functions by available devices: a new algorithm.	VLSI Design	1995	DBLP DOI BibTeX RDF	design functions, available devices, function behaviors, mapping process, VLSI, VLSI, CAD, finite state machines, finite state machines, logic CAD, circuit CAD, logic partitioning, logic partitioning
1	Puneet Sawhney, Haroon Rasheed	Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array.	VLSI Design	1995	DBLP DOI BibTeX RDF	static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators
1	Khushro Shahookar, Pinaki Mazumder	Genetic multiway partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	genetic multiway partitioning, result quality, binary chromosome, bit-mask operations, net cut evaluation, MCNC benchmark circuits, cut size, genetic algorithms, VLSI, VLSI, CAD, software tools, software tool, logic CAD, mutation, circuit CAD, crossover, cellular arrays, cost function, circuit optimisation, logic partitioning, multiple objectives, bipartitioning
1	Sven Simon, Ralf Bucher, Josef A. Nossek	Retiming of synchronous circuits with variable topology.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits
1	Anoop Singhal, Chi-Yuan Lo	Object oriented data modeling for VLSI/CAD.	VLSI Design	1995	DBLP DOI BibTeX RDF	design data manager, integrated CAD system, modular program architecture, VLSI, object-oriented methods, integrated circuit design, circuit CAD, object oriented data modeling, VLSI CAD
1	Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana	CODAC-a characterization system for digital and analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	CODAC, characterization system, electrical simulator, procedural interface, customized analysis functions, parallel processing, circuit analysis computing, Monte Carlo methods, circuit CAD, SPICE, SPICE, analog circuits, digital circuits, CAD tool, digital integrated circuits, analogue integrated circuits, circuit analysis, Monte Carlo analysis
1	Trevor J. Smedley	A High-Level Visual Language for the Graphical Description of Digital Circuits. (PDF / PS)	VL	1995	DBLP DOI BibTeX RDF	pulse circuits, high-level visual language, graphical description, programming language systems, digital design systems, full-featured visual programming language, complex circuit specification, repetitive structures, conditional structures, visual languages, circuit analysis computing, circuit CAD, digital circuits, engineering graphics, program structures, digital circuit design
1	B. Hamdi, Hakim Bederr, Michael Nicolaidis	A tool for automatic generation of self-checking data paths.	VTS	1995	DBLP DOI BibTeX RDF	self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers
1	Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang	Addressing high frequency effects in VLSI interconnects with full wave model and CFH.	ICCAD	1995	DBLP DOI BibTeX RDF
1	Fred J. Meyer, Dhiraj K. Pradhan	Modeling Defect Spatial Distribution.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	defect spatial distribution modelling, center-satellite model, wafers, redundancy techniques, cluster, VLSI, fault tolerant computing, circuit CAD, fault-tolerant designs, yield models, WSI
1	Akio Okazaki, Takashi Kondo, Kazuhiro Mori, Shou Tsunekawa, Eiji Kawamoto	An Automatic Circuit Diagram Reader with Loop-Structure-Based Symbol Recognition.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	automatic circuit diagram reader, loop-structure-based symbol recognition, logic circuit diagram reader, symbol segmentation, symbol identification, decision-tree control, character string recognition, connecting line analysis, computer vision, feature extraction, computerised pattern recognition, computerised pattern recognition, logic CAD, template matching, circuit CAD, VLSI-CAD
1	F. Matthew Rhodes, Joseph J. Dituri, Glenn H. Chapman, Bruce E. Emerson, Antonio M. Soares, Jack I. Raffel	A Monolithic Hough Transform Processor Based on Restructurable VLSI.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	pixel grouping, WSI technology, monolithic Hough transform processor, restructurable VLSI, wafer-scale-integration technology, PC board, monolithic integrated circuits, image processing, VLSI, transforms, computerised pattern recognition, digital arithmetic, circuit CAD, microprocessor chips, CAD tools, PCB, linear feature extraction
1	P. Sadayappan, V. Visvanathan	Circuit Simulation on Shared-Memory Multiprocessors.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	vector multiprocessor, sparse matrix solution, parallel processing, parallelization, shared-memory multiprocessors, digital simulation, circuit CAD, circuit simulator, parallel implementation