Search results for "circuit analysis computing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
1	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	Compaction-based test generation using state and fault information.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
1	Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang	A realistic fault model for flash memories.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	NAND circuits, faulty behavior classification, NAND-type flash memory, SPICE models, flash cell models, circuit-level faulty behavior simulation, testing, fault model, fault modeling, fault simulation, flash memories, flash memories, circuit analysis computing, SPICE, integrated memory circuits
1	Bin Liu, Fabrizio Lombardi, Wei-Kang Huang	Testing programmable interconnect systems: an algorithmic approach.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
1	Tuyen V. Nguyen, Anirudh Devgan	State transformation in event driven explicit simulation.	ICCAD	1997	DBLP DOI BibTeX RDF	event driven explicit simulation, state equation, state representation, state transformation, circuit analysis computing, simulation algorithm, similarity transformation
1	Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel	Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation.	Workshop on Parallel and Distributed Simulation	1997	DBLP DOI BibTeX RDF	asynchronous parallel algorithms, dynamic characteristics, redundant work, sequential VLSI circuits, synchronous two stage approach, test set partitioned fault simulation, MPI, Message Passing Interface, shared memory multiprocessor, circuit analysis computing, circuit CAD, software portability
1	Abby A. Ilumoka	Modular artificial neural network models for simulation and optimization of VLSI circuits.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	modular artificial neural network models, MANN, process level parameters, optimization, circuit analysis computing, VLSI circuits, modular neural network, circuit performance
1	Vamsi Boppana, W. Kent Fuchs	Integrated fault diagnosis targeting reduced simulation.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS 85 circuit, ISCAS 89 circuit, dynamic techniques, integrated fault diagnosis, precomputed information, reduced simulation, run-time cost reduction, static techniques, combinational circuit, circuit analysis computing, run-time analysis
1	Chung-Ping Chen, Hai Zhou, D. F. Wong	Optimal non-uniform wire-sizing under the Elmore delay model.	ICCAD	1996	DBLP DOI BibTeX RDF	Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation
1	Guowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar	An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data.	ICCAD	1996	DBLP DOI BibTeX RDF	complex frequency hopping algorithm, generalized stencil, linear subnetworks, measured data, moment-generation algorithm, moment-matching simulation, tabulated data, circuit analysis computing, circuit simulators, time-domain analysis
1	Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet	A symbolic simulation approach in resolving signals' correlation.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools
1	Ayman I. Kayssi	Macromodeling C- and RC-loaded CMOS inverters for timing analysis.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling
1	Come Rozon	On the Use of VHDL as a Multi-Valued Logic Simulator. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications
1	Hao Tang, Hung Chang Lin	Multi-Valued Decoder Based on Resonant Tunneling Diodes in Current Tapping Mode. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued decoder, current tapping mode, single peaked RTD sections, single literal function, simulation, decoding, circuit analysis computing, multivalued logic circuits, resonant tunnelling diodes, resonant tunneling diodes
1	Georgios K. Theodoropoulos, J. V. Woods	Simulating Asynchronous Architectures on Transputer Networks.	PDP	1996	DBLP DOI BibTeX RDF	asynchronous architecture simulation, asynchronous design techniques, clock related timing problems, CSP based parallel language, asynchronous architectural simulation models, parallel architectures, logic design, asynchronous circuits, circuit analysis computing, parallel languages, Occam, Occam, asynchronous logic, transputer systems, transputer networks
1	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Parallel concurrent path-delay fault simulation using single-input change patterns.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations
1	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
1	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	On test coverage of path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
1	Pradip Mandal, V. Visvanathan	Design of high performance two stage CMOS cascode op-amps with stable biasing.	VLSI Design	1996	DBLP DOI BibTeX RDF	two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability
1	Rajesh Ramadoss, Michael L. Bushnell	Test generation for mixed-signal devices using signal flow graphs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
1	S. Sundaram, Lalit M. Patnaik	Distributed logic simulation: time-first evaluation vs. event driven algorithms.	VLSI Design	1996	DBLP DOI BibTeX RDF	distributed logic simulation, time-first evaluation algorithm, event driven algorithm, digital circuit simulation, distributed simulation algorithms, parallel algorithms, parallel processing, VLSI, logic CAD, circuit analysis computing, integrated logic circuits, VLSI circuits, parallel logic simulation
1	Chuan-Yu Wang, Kaushik Roy	Maximum power estimation for CMOS circuits using deterministic and statistic approaches.	VLSI Design	1996	DBLP DOI BibTeX RDF	maximum power estimation, deterministic approach, instantaneous power consumption, ATG technique, Monte Carlo based technique, computational complexity, VLSI, lower bound, statistical analysis, automatic testing, circuit analysis computing, Monte Carlo methods, automatic test generation, VLSI circuits, CMOS circuits, CMOS digital integrated circuits, statistic approach
1	Minesh B. Amin, Bapiraju Vinnakota	ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator.	VTS	1996	DBLP DOI BibTeX RDF	ZAMBEZI, parallel pattern simulator, parallel fault simulation, sequential circuit fault simulator, multiple faults simulation, multiple vectors, parallel algorithms, VLSI, fault diagnosis, logic testing, sequential circuits, circuit analysis computing, integrated logic circuits
1	Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs	Full fault dictionary storage based on labeled tree encoding.	VTS	1996	DBLP DOI BibTeX RDF	digital storage, full fault dictionary storage, labeled tree encoding, fault dictionary compaction, binary string code, implicit storage, VLSI, fault diagnosis, logic testing, integrated circuit testing, encoding, automatic testing, circuit analysis computing, fault trees
1	Sreejit Chakravarty	A sampling technique for diagnostic fault simulation.	VTS	1996	DBLP DOI BibTeX RDF	diagnostic fault simulation, diagnostic test sets, EC/IC Sampling, indistinguishable classes, approximation algorithm, fault diagnosis, integrated circuit testing, circuit analysis computing, set theory, equivalence classes, equivalence classes, sampling technique
1	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Segment delay faults: a new fault model.	VTS	1996	DBLP DOI BibTeX RDF	segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects
1	F. Mohamed, M. Manzouki, Anton Biasizzo, Franc Novak	Analog circuit simulation and troubleshooting with FLAMES.	VTS	1996	DBLP DOI BibTeX RDF	analog circuit simulation, model-based expert system, VLSI, fuzzy logic, fuzzy logic, integrated circuit testing, circuit analysis computing, analogue integrated circuits, troubleshooting, FLAMES, diagnostic expert systems
1	John W. Sheppard, William R. Simpson	Improving the accuracy of diagnostics provided by fault dictionaries.	VTS	1996	DBLP DOI BibTeX RDF	diagnostics accuracy improvement, digital circuit diagnosis, information flow model, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, circuit analysis computing, digital integrated circuits, fault dictionaries, nearest neighbor classification
1	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
1	Pranav Ashar, Sharad Malik	Fast functional simulation using branching programs.	ICCAD	1995	DBLP DOI BibTeX RDF	compiled code simulation, cycle-based functional simulation, fast functional simulation, functional delay-independent logic simulation, levelized compiled-code, switch level functional simulation, synchronous digital systems, Boolean functions, system design, logic design, logic CAD, decision theory, circuit analysis computing, benchmark circuits, branching programs
1	Mike Chou, Jacob K. White	Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect.	ICCAD	1995	DBLP DOI BibTeX RDF	Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics)
1	Edmund M. Clarke, Masahiro Fujita, Xudong Zhao	Hybrid decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	MTBDDs, arithmetic circuits verification, boolean vectors, hybrid decision diagrams, linear expressions, multi-terminal binary decision diagrams, symbolic model checking algorithms, computational complexity, time complexity, digital arithmetic, binary decision diagrams, circuit analysis computing, integers, BMDs
1	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
1	K. K. Lai, P. H. W. Leong	An area efficient implementation of a cellular neural network.	ANNES	1995	DBLP DOI BibTeX RDF	area efficient implementation, time multiplexing scheme, higher density implementations, neural circuits, simulation, VLSI, edge detection, edge detection, circuit analysis computing, VLSI circuits, cellular neural network, neural chips, cellular logic, cellular neural nets
1	Youngmin Hur, Stephen A. Szygenda	Special purpose array processor for digital logic simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost
1	Glenn Jennings	Accurate ternary-valued compiled logic simulation of complex logic networks by OTDD composition.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	circuit diagrams, ternary-valued compiled logic simulation, complex logic networks, OTDD composition, combinational U inaccuracies, reconvergent fanout, Kleenean strong ternary logic, Ordered Ternary Decision Diagram, standard ISCAS 85 benchmarks, performance evaluation, logic CAD, digital simulation, circuit analysis computing, ternary logic, incompletely-specified functions
1	Krishna Kant	Performance of internal overload controls in large switches.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	internal overload control performance, large switches, switch sizes, call capacity, voice circuits, overload performance, network integrity, peripheral scanning schemes, scheduling, performance evaluation, virtual machines, logic CAD, circuit analysis computing, simulation model, service integrity, buffer sizes, switching circuits
1	Volkhard Klinger	DiPaCS: a new concept for parallel circuit simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	DiPaCS system, parallel circuit simulation, distributed parallel circuit simulator, integrated circuit simulation, hierarchical circuit simulator, parallel processing, parallel programming, iterative methods, parallel machines, circuit analysis computing, integrated circuit layout, multicomputer systems, parallel iterative method
1	C. Rominger, Jean Claude Geffroy	Hazard analysis of structured sequential systems.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	structured sequential systems, time uncertainties, asynchronous sequential systems, nondeterministic phenomena, simulation method, structured systems, fault diagnosis, CAD, logic testing, timing, sequential circuits, logic CAD, asynchronous circuits, digital simulation, time analysis, circuit analysis computing, hazard analysis, asynchronous sequential logic
1	A. K. B. A'ain, A. H. Bratt, A. P. Dorey	On the development of power supply voltage control testing technique for analogue circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	power supply circuits, voltage control, power supply voltage control testing, hard defects, soft defects, simulation, fault diagnosis, integrated circuit testing, data analysis, data analysis, circuit analysis computing, operational amplifiers, operational amplifier, analogue integrated circuits, IC tests, analogue circuits
1	Winfried Hahn, Andreas Hagerer, R. Kandlbinder	Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hardware-accelerated concurrent fault simulation, eventflow computing, highly-parallel Munich Simulation Computer, compiler-driven simulation, selective trace simulation, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, discrete event simulation, MuSiC, automatic testing, automatic testing, circuit analysis computing, logic simulation, concurrent engineering, test vectors, data flow computing, dataflow computing
1	Eiji Harada, Janak H. Patel	Overhead reduction techniques for hierarchical fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI
1	Chen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin	Fast fault simulation for BIST applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	signature computation, BIST applications, combinational fault simulation, BISTSIM, demand-driven logic simulation algorithm, fault propagation methods, bit-array computation, parallel-pattern sequential simulation, speedup ratio, VLSI, VLSI, logic testing, built-in self test, integrated circuit testing, combinational circuits, digital simulation, circuit analysis computing, aliasing, test patterns, MISR
1	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck	On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple stuck-at fault simulation, multiple domain simulation, comparative simulation, MDCCS, discrete event concurrent simulation, CPU time efficiency, digital logic fault simulation, fault diagnosis, logic testing, discrete event simulation, circuit analysis computing, fault location, concurrent engineering
1	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
1	Michel Renovell, P. Huc, Yves Bertrand	Serial transistor network modeling for bridging fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	serial transistor network modeling, voting model, biased voting model, relative transistor strength, SPICE pre-simulation, fault simulation procedure, CMOS logic, fault diagnosis, logic testing, integrated circuit testing, digital simulation, circuit analysis computing, CMOS logic circuits, SPICE, integrated circuit modelling, bridging fault simulation
1	Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey	A simple technique for locating gate-level faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
1	Garth Baulch, David Hemmendinger, Cherrice Traver	Analyzing and verifying locally clocked circuits with the concurrency workbench.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	locally clocked circuits, concurrency workbench, synchronous computational elements, concurrent system modelling, CCS process algebra, formal verification, timing, logic design, process algebra, logic CAD, asynchronous circuits, asynchronous circuits, circuit analysis computing, asynchronous communication
1	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
1	Nestoras Tzartzanis, William C. Athas	Design and analysis of a low-power energy-recovery adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
1	K. Y. Wu, P. K. H. Ng, Xing Dong Jia, Richard M. M. Chen, A. M. Layfield	Performance tuning of a multiprocessor sparse matrix equation solver.	HICSS	1995	DBLP DOI BibTeX RDF	multiprocessor sparse matrix equation solver, sparse matrix equation, linear simultaneous equations, electrical circuit, multiprocessor implementation, parallel direct method, parallel algorithms, circuit analysis computing, SPICE, SPICE, circuit simulation, sparse matrices, performance tuning
1	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
1	Minesh B. Amin, Bapiraju Vinnakota	Data parallel fault simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	data parallel fault simulation, compute intensive problem, fault simulation time, fault set partitioning technique, low cost parallel resource, logic gate level, parallel programming, fault diagnosis, logic testing, logic CAD, circuit analysis computing, workstations, logic partitioning, multiple processors
1	Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs	Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling
1	Kai-Yuan Chao, D. F. Wong	Thermal placement for high-performance multichip modules. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	thermal placement, high-performance multichip modules, electrical performance requirements, thermal behavior, high-speed chips, multichip module packages, cooling environments, conduction cooling, convection cooling, chip junction temperatures, circuit analysis computing, multichip modules, thermal models, cooling, convection
1	Ajay J. Daga, William P. Birmingham	A symbolic-simulation approach to the timing verification of interacting FSMs. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	symbolic-simulation approach, interacting FSMs, timing verifier, complex sequential circuit verification, combinational paths, inherently modular nature, symbolic simulation verification methodology, formal verification, logic testing, finite state machines, finite state machines, sequential circuits, circuit analysis computing, timing verification
1	Alexander Dalal, Lavi Lev, Sundari Mitra	Design of an efficient power distribution network for the UltraSPARC-I microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network
1	Anirudh Devgan	Accurate device modeling techniques for efficient timing simulation of integrated circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models
1	Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda	Statistics on concurrent fault and design error simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	concurrent fault/design error simulation, design error simulation processes, c-sim, gate level concurrent simulator, event based statistics, gate evaluation statistics, simulator developers, hardware accelerator designers, design options, parallel algorithms, formal verification, circuit analysis computing, design verification, memory requirements, experimental data, concurrent simulators
1	Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham	Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	control flow machine, verification vectors, formal verification, logic testing, digital simulation, circuit analysis computing, design verification, functional specification
1	Michael S. Hsiao, Janak H. Patel	A new architectural-level fault simulation using propagation prediction of grouped fault-effects. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	architectural-level fault simulation, propagation prediction, grouped fault-effects, fault effects, intelligent propagation prediction, automated behavioral simulation, ALFSIM, Architectural Level Fault Simulation, gate level fault simulation, VLSI, fault diagnosis, circuit analysis computing, stuck at faults, integrated circuit design, deterministic algorithm, data types, symbolic data, architectural level
1	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
1	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
1	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS . (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
1	C. Truzzi, Eric Beyne, E. Ringoot, J. Peeters	Signal propagation in high-speed MCM circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	thin film circuits, signal propagation, high-speed MCM circuits, thin-film multichip module substrate, timing analyses, lossy interconnection lines, timing, circuit analysis computing, circuit simulations, CMOS integrated circuits, CMOS integrated circuits, multichip modules, receivers, drivers, microsystems, substrates
1	Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai	Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	coupled transmission lines, frequency-dependent losses, scattering-parameter based macromodel, S-parameter macromodel based simulator, circuit analysis computing, transient analysis, transient analysis, transmission lines, losses, S-parameters
1	Jin-Tai Yan	Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	fuzzy neural nets, connection-oriented net model, fuzzy clustering techniques, K-way circuit partitioning, chain net model, cut analysis, multiple-pin net, edge-weighted graph, MCNC circuit benchmarks, partitioning balance, partitioning cut, computational complexity, complexity, fuzzy logic, high level synthesis, circuit analysis computing, hypergraph, fuzzy c-means clustering, mapped graph, fuzzy memberships
1	Hideaki Doi, Yoko Suzuki, Yasuhiko Hara, Tadashi Iida, Yasuhiro Fujishita, Koichi Karasaki	Real-Time X-Ray Inspection of 3D Defects in Circuit Board Patterns. (PDF / PS)	ICCV	1995	DBLP DOI BibTeX RDF	printed circuit layout, X-ray applications, real time X-ray inspection, real-time X-ray inspection, 3D defect, 3-D defects, circuit board patterns, three dimensional defects, fine PCB patterns, sphere surface, X-ray detector, defect detection algorithm, heavy shading, real-time systems, feature extraction, feature extraction, signal processing, inspection, circuit analysis computing, X-ray images, printed circuit board, printed circuit testing, perspective transform, intensity variation, defect detection techniques
1	Timothy J. McBrayer, Philip A. Wilsey	Process combination to increase event granularity in parallel logic simulation. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	event granularity, VHDL description, parallel processing, logic CAD, circuit analysis computing, logic circuits, logic circuits, symmetric multiprocessors, logic simulation, digital system design, parallel logic simulation, parallel logic simulators
1	Rolf Drechsler, Rolf Krieger, Bernd Becker	Random Pattern Fault Simulation in Multi-Valued Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	random pattern fault simulation, multi-valued circuits, multi-valued logic networks, fault diagnosis, logic testing, integrated circuit testing, fault simulator, circuit analysis computing, multivalued logic circuits, random pattern testability
1	Elena Dubrova, Dilian Gurov, Jon C. Muzio	The Evaluation of Full Sensitivity for Test Generation in MVL Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	full sensitivity evaluation, MVL circuits, functional level, m-valued n-variable functions, multi-valued logic circuits, fault diagnosis, logic testing, test generation, circuit analysis computing, multivalued logic circuits
1	Michael Goedecke, Sorin A. Huss, Kai Morich	Automatic Parallelization of the Visual Data-Flow Language Cantata for Efficient Characterization of Analog Circuit Behavior. (PDF / PS)	VL	1995	DBLP DOI BibTeX RDF	engineering workstations, Cantata visual data-flow language, analog circuit behavior characterisation, application specific functions, execution time reduction, data-flow scheduler, usable workstations, usable workstation performance, program availability, fully automated process, simulation, computational complexity, load balancing, parallel programming, resource allocation, visual languages, digital simulation, processor scheduling, circuit analysis computing, workloads, automatic parallelization, parallel languages, distributed environment, workstations, analogue circuits, control operators
1	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
1	George A. Hadgis, P. R. Mukund	A novel CMOS monolithic analog multiplier with wide input dynamic range.	VLSI Design	1995	DBLP DOI BibTeX RDF	analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits
1	Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh	A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology.	VLSI Design	1995	DBLP DOI BibTeX RDF	integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation
1	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
1	Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana	CODAC-a characterization system for digital and analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	CODAC, characterization system, electrical simulator, procedural interface, customized analysis functions, parallel processing, circuit analysis computing, Monte Carlo methods, circuit CAD, SPICE, SPICE, analog circuits, digital circuits, CAD tool, digital integrated circuits, analogue integrated circuits, circuit analysis, Monte Carlo analysis
1	Trevor J. Smedley	A High-Level Visual Language for the Graphical Description of Digital Circuits. (PDF / PS)	VL	1995	DBLP DOI BibTeX RDF	pulse circuits, high-level visual language, graphical description, programming language systems, digital design systems, full-featured visual programming language, complex circuit specification, repetitive structures, conditional structures, visual languages, circuit analysis computing, circuit CAD, digital circuits, engineering graphics, program structures, digital circuit design
1	Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò	Reliability evaluation of combinational logic circuits by symbolic simulation.	VTS	1995	DBLP DOI BibTeX RDF	mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
1	Tapan J. Chakraborty, Vishwani D. Agrawal	Simulation of at-speed tests for stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
1	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
1	Peter Lidén, Peter Dahlgren	Switch-level modeling of transistor-level stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling
1	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
1	Rajesh Nair, Dong Sam Ha	VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	parallel pattern fault simulator, VLSI, VLSI, fault diagnosis, heuristics, logic testing, integrated circuit testing, sequential circuits, digital simulation, VISION, circuit analysis computing, flip-flops, synchronous sequential circuits, benchmark circuits
1	Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang	Addressing high frequency effects in VLSI interconnects with full wave model and CFH.	ICCAD	1995	DBLP DOI BibTeX RDF
1	Hussein M. Alnuweiri	Optimal VLSI Networks for Multidimensional Transforms.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	optimal VLSI networks, multidimensional transforms, AT/sup 2/-optimal networks, mapping large K-shuffle networks, index-rotation operations, regular layouts, VLSI, fast Fourier transforms, discrete Fourier transform, circuit analysis computing, minimisation of switching nets
1	Takushi Tanaka	Parsing Electronic Circuits in a Logic Grammar.	IEEE Trans. Knowl. Data Eng.	1993	DBLP DOI BibTeX RDF	trouble shooting, automatic circuit understanding, circuit structures, definite clause set grammar, DCSG top-down parsing mechanism, trees (mathematics), circuit analysis computing, grammars, structural analysis, formal logic, hierarchical structures, circuit design, words, parse trees, functional blocks, causal analysis, sentence, logic grammar
1	Yuval Tamir, Hsin-Chou Chi	Symmetric Crossbar Arbiters for VLSI Communication Switches.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	VLSI communication switches, symmetric crossbar arbiters, multistage interconnectionnetwork, switch arbitration policy, worst-case latency, circuitsimulation, performance evaluation, VLSI, circuit analysis computing, network simulations, critical path, multiprocessorinterconnection networks, system clock
1	Franz Fink, Karl Fuchs, Michael H. Schulz	Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	path delay fault simulation, parallel processing, parallel processing, patterns, integrated circuit testing, circuit analysis computing, fault location, many-valued logics
1	Rohit Kapur, M. Ray Mercer	Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	bounding algorithm, circuit faults, conditional syndromes, auxiliary gate, pseudorandom pattern resistant faults, circuit structure, computational complexity, lower bounds, built-in self test, integrated circuit testing, circuit analysis computing, signal probabilities, testability measurement, random pattern testability
1	John P. Fishburn	Clock Skew Optimization.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	synchronous digital system, minimum safety margin, performance, linear programs, optimisation, CMOS, circuit analysis computing, flip-flops, circuit simulation, CMOS integrated circuits, path delays, clock signal
1	Lindsay Kleeman	The Jitter Model for Metastability and Its Application to Redundant Synchronizers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	jitter model, redundant synchronizers, circuit noise, CMOS D-type flip-flop, bistable device, simulation, circuit analysis computing, flip-flops, SPICE, CMOS integrated circuits, integrated logic circuits, reliability analysis, metastability, timing model, circuit analysis
1	Yasuhiko Hara, Hideaki Doi, Koichi Karasaki, Tadashi Iida	A System for PCB Automated Inspection Using Fluorescent Light.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	violet illumination, PCB automated inspection, fluorescent light, nicks, printed circuit board pattern, ultraviolet rays, glass-epoxy, glass-polyimide, high-sensitivity TV camera, silhouette image, fluorescence, pattern recognition, computer vision, computer vision, fault detection, computerised pattern recognition, inspection, circuit analysis computing, fault location, cuts, printed circuit testing, optical fiber, short-circuits
1	D. B. Shu, C. C. Li, J. F. Mancuso, Y. N. Sun	A Line Extraction Method for Automated SEM Inspection of VLSI Resist.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	line extraction method, automated SEM inspection, VLSI resist, precision digital edge-line-detection method, edge contours, submicrometer width, integrated circuit fabrication, computer vision, VLSI, transforms, integrated circuit testing, computerised picture processing, automatic testing, Hough transform, inspection, circuit analysis computing, scanning electron microscopy, scanning electron microscopy
1	Haruo Yoda, Yozo Ohuchi, Yuzo Taniguchi, Masakazu Ejiri	An Automatic Wafer Inspection System Using Pipelined Image Processing Techniques.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	automatic wafer inspection system, pipelined image processing techniques, defective patterns, multilayered wafer patterns, comparison method, digital design pattern data, CAD data, 6 micron, 7 MHz, pattern recognition, computer vision, computer vision, picture processing, integrated circuit testing, computerised picture processing, computerised pattern recognition, inspection, circuit analysis computing, fault location, pipeline processing, defect detection, defect classification, false-alarm rate