Search results for "circuit architectures"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Carlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici	Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces.	DATE	2008	DBLP DOI BibTeX RDF
2	Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny	Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup.	AICT/ICIW	2006	DBLP DOI BibTeX RDF
1	Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya	Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator.	IJUC	2011	DBLP BibTeX RDF
1	Sergio Callegari	Introducing Complex Oscillation Based Test: an application example targeting Analog to Digital Converters.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny	Design and analysis of matching circuit architectures for a closest match lookup.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Ajay K. Verma, Paolo Ienne	Towards the automatic exploration of arithmetic-circuit architectures.	DAC	2006	DBLP DOI BibTeX RDF
1	Satoshi Sugahara, Masaaki Tanaka	Spin MOSFETs as a basis for spintronics.	TOS	2006	DBLP DOI BibTeX RDF	spin MOSFETs, spin transistors, MOSFETs, Spintronics
1	Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas	Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.	DELTA	2006	DBLP DOI BibTeX RDF
1	Noam Dolev, Avner Kornfeld, Avinoam Kolodny	Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology.	Journal of Circuits, Systems, and Computers	2005	DBLP DOI BibTeX RDF
1	David Blaauw, Anirudh Devgan, Farid N. Najm	Leakage power: trends, analysis and avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Yushan Li, Dragan Maksimovic	High efficiency wide bandwidth power supplies for GSM and EDGE RF power amplifiers.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen	Case study of interconnect analysis for standing wave oscillator design.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	MOS current mode circuits: analysis, design, and variability.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Ying Yi, Roger Woods, Lok-Kee Ting, C. F. N. Cowan	High Speed FPGA-Based Implementations of Delayed-LMS Filters.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	delayed LMS filters, retiming technique, hardware sharing, FPGA, adaptive filtering
1	Gladys Omayra Ducoudray, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	High-speed high-precision analog rank order filter in CMOS technology.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Silvio Misera, Heinrich Theodor Vierhaus	FIT - A Parallel Hierarchical Fault Simulation Environment.	PARELEC	2004	DBLP DOI BibTeX RDF
1	John McAllister, Roger Woods, Richard L. Walke	Embedded Context Aware Hardware Component Generation for Dataflow System Exploration.	SAMOS	2004	DBLP DOI BibTeX RDF
1	James R. Heath	A systems approach to molecular electronics.	ISLPED	2003	DBLP DOI BibTeX RDF
1	Toshifumi Enomoto, Tomohito Ei	Low-power CMOS circuit techniques for motion estimators.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Gaye Lightbody, Roger Woods, Richard L. Walke	Design of a parameterizable silicon intellectual property core for QR-based RLS filtering.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Morten Hartmann, Pauline C. Haddow, Frode Eskelund	Evolving Robust Digital Designs.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
1	Régis Leveugle, R. Cercueil	High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	circuit architectures, fault tolerance, VHDL, on-line testing
1	Seng-Pan U., Rui Paulo Martins, José E. Franca	A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Hannu Tenhunen, Elena Dubrova	SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH. (PDF / PS)	MSE	2001	DBLP DOI BibTeX RDF
1	Sree Ganesan, Ranga Vemuri	Library Binding for High-Level Synthesis of Analog Systems.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Christian Pacha, U. Auer, C. Burwick, Peter Glösekötter, A. Brennemann, Werner Prost, Franz-Josef Tegude, K. F. Goser	Threshold logic circuit design of parallel adders using resonant tunneling devices.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
1	Seng-Pan U., Rui Paulo Martins, José E. Franca	Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity.	ISCAS	1999	DBLP DOI BibTeX RDF
1	David W. Trainor, Roger F. Woods, John V. McCanny	Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS".	VLSI Signal Processing	1997	DBLP DOI BibTeX RDF
1	Jeffrey C. Gealow, F. P. Herrmann, L. T. Hsu, Charles Sodini	System design for pixel-parallel image processing.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF