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Results
Found 5 publication records. Showing 5 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Shuo-Hsien Hsiao, C. Y. Roger Chen |
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy.  |
IEEE Trans. Parallel Distrib. Syst.  |
1992 |
DBLP DOI BibTeX RDF |
message size, circuit switched multistage interconnection networks, hold strategy, processor-memory communications, processor processing time, closed queuing network model, performance evaluation, performance evaluation, multiprocessor interconnection networks, queueing theory, multiprocessor systems, switching theory, memory access |
| 1 | Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos |
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. |
EDCC |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | C. Y. Roger Chen, Shuo-Hsien Hsiao, Abdulaziz S. Almazyad |
A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks. |
IEEE/ACM Trans. Netw. |
1995 |
DBLP DOI BibTeX RDF |
performance evaluation, queueing theory, multistage interconnection networks, circuit switching |
| 1 | Shuo-Hsien Hsiao, C. Y. Roger Chen |
A New Model for the Performance Evaluation of Synchronous Circuit Switched Multistage Interconnection Networks. |
IPPS |
1993 |
DBLP BibTeX RDF |
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| 1 | Nathaniel J. Davis IV, Howard Jay Siegel |
The Performance Analysis of Partitioned Circuit Switched Multistage Interconnection Networks. |
ISCA |
1985 |
DBLP DOI BibTeX RDF |
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