Search results for "circuit tuning"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich	The opportunity cost of low power design: a case study in circuit tuning.	ISLPED	2009	DBLP DOI BibTeX RDF	low power design, productivity, circuit tuning
3	Mohamed A. El-Gamal, Hany L. Abdel-Malek, M. A. Sorour	A neural-network-based approach for post-fabrication circuit tuning.	Neural Computing and Applications	2005	DBLP DOI BibTeX RDF	Clustering, Neural networks, Feature selection, Self organizing maps, Circuit tuning
2	Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu	Circuit optimization via adjoint Lagrangians.	ICCAD	1997	DBLP DOI BibTeX RDF	Adjoint circuit, Optimization, Circuit simulation, Trust region, Augmented Lagrangian, Circuit tuning
1	Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	Transistor sizing of custom high-performance digital circuits with parametric yield considerations.	DAC	2010	DBLP DOI BibTeX RDF	custom circuits, optimization
1	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
1	Kevin Brownell, Gu-Yeon Wei, David Brooks	Evaluation of voltage interpolation to address process variations.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan	Structured and tuned array generation (STAG) for high-performance random logic.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	programmable logic arrays (PLAs), design automation
1	Mohamed A. El-Gamal, Hany L. Abdel-Malek, M. A. Sorour	Automatic Circuit Tuning via Unsupervised Learning Paradigms.	Journal of Circuits, Systems, and Computers	2006	DBLP DOI BibTeX RDF
1	Kambiz Rahimi, Chris Diorio	Design and Application of Adaptive Delay Sequential Elements.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Andreas Wächter, Chandramouli Visweswariah, Andrew R. Conn	Large-scale nonlinear optimization in circuit tuning.	Future Generation Comp. Syst.	2005	DBLP DOI BibTeX RDF
1	Kambiz Rahimi, Chris Diorio	In-Circuit Self-Tuning of Clock Latencies.	ISQED	2005	DBLP DOI BibTeX RDF
1	Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski	Uncertainty-aware circuit optimization.	DAC	2002	DBLP DOI BibTeX RDF	small uncertainty, optimization, process variation, nonlinear, performance optimization, transistor sizing, circuit tuning
1	Andrew R. Conn, Chandramouli Visweswariah	Overview of continuous optimization advances and applications to circuit tuning.	ISPD	2001	DBLP DOI BibTeX RDF
1	Phillip Restle, Albert E. Ruehli, Steven G. Walker	Multi-GHz interconnect effects in microprocessors.	ISPD	2001	DBLP DOI BibTeX RDF	full-wave analysis, simulation, interconnect, inductance, extraction, clock distribution, circuit-tuning
1	George Gristede, Wei Hwang	A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
1	Yngvar Berg, Tor Sverre Lande	Area efficient circuit tuning with floating-gate techniques.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Chandramouli Visweswariah	Optimization techniques for high-performance digital circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	nonlinear optimization, gradients, adjoints, circuit tuning
1	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah	Optimization of custom MOS circuits by transistor sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	simulation, optimization, Circuits, gradients, transistor sizing