Search results for "clock"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Vernon L. Chi	Salphasic Distribution of Clock Signals for Synchronous Systems.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	transmission line theory, loaded transmission line, printed circuit board clock planes, clock plane, phase skew, salphasic clock, synchronisation, clocks, distribution network, clock skews, synchronous systems, synchronous system, propagation delay, system clock, phase shifts, clock signals, clock signal
6	Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Timing-driven variation-aware nonuniform clock mesh synthesis.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution
6	Amor Bouzelat, Zoubir Mammeri	Simple reading, implicit rejection and average function for fault-tolerant physical clock synchronization.	EUROMICRO	1997	DBLP DOI BibTeX RDF	simple reading, implicit rejection, average function, fault tolerant physical clock synchronization algorithms, remote clock reading function, fault value rejection function, convergence function, clock adjustment function, clock value reference set, Lundelius algorithm, reference set, maximum skew, fault tolerance, distributed algorithms, synchronization algorithms
6	Alan Olson, Kang G. Shin	Fault-Tolerant Clock Synchronization in Large Multicomputer Systems.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	fault-tolerant clock synchronization, large multicomputer systems, clock value, maximum skew, maximum time, fault tolerance, reliability, fault tolerant computing, multiprocessing systems, synchronisation, clocks, clock skew, clock drift, synchronization algorithm
6	Daniel L. Palumbo	The Derivation and Experimental Verification of Clock Synchronization Theory.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	clock synchronization theory, Interactive Convergence Clock Synchronization Algorithm, Mid-Point Algorithm, clock circuitry, operating conditions, worst case failures, experimental verification, formal methods, formal verification, synchronisation, clock synchronization, clock skew, byzantine failure, proof of correctness, failure modes, timing circuits, malicious failures
5	Martin Saint-Laurent, Animesh Datta	A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.	ISLPED	2010	DBLP DOI BibTeX RDF	clock gater, clock gating cell, local clock buffer, set-reset latch
5	Benjamin R. Hamilton, Xiaoli Ma, Qi Zhao, Jun Xu	ACES: adaptive clock estimation and synchronization using Kalman filtering.	MOBICOM	2008	DBLP DOI BibTeX RDF	clock offset, resource-constrained network, Kalman filter, clock synchronization, clock skew
5	Lain-Chyr Hwang, Steen J. Hsu, San-Yuan Wang, Yong-Hua Huang	A Hybrid Scheduling Algorithm with Low Complexity: Jumping Virtual Clock Round Robin.	ICDCS Workshops	2005	DBLP DOI BibTeX RDF	Jumping Virtual Clock (JVC), Jumping Virtual Clock Round Robin (JVCRR), Scheduling algorithm, Fair queueing, Round Robin, Virtual clock
5	Chung-Seok (Andy) Seo, Abhijit Chatterjee, Sang-Yeon Cho, Nan M. Jokerst	Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	H-tree, asymmetric structure, optical clock distribution, optical waveguide loss modeling, optoelectronic system-on-a-package, optimization, clock distribution, clock routing
5	Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi	A practical clock tree synthesis for semi-synchronous circuits.	ISPD	2000	DBLP DOI BibTeX RDF	clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling
5	Peter Wohl, John A. Waicukauski	Using ATPG for clock rules checking in complex scan design.	VTS	1997	DBLP DOI BibTeX RDF	clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification
5	Joe G. Xi, Wayne Wei-Ming Dai	Jitter-tolerant clock routing in two-phase synchronous systems.	ICCAD	1996	DBLP DOI BibTeX RDF	Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
5	H. Hao, K. Bhabuthmal	Clock controller design in SuperSPARC II microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller
4	Ashutosh Chakraborty, David Z. Pan	Skew management of NBTI impacted gated clock trees.	ISPD	2010	DBLP DOI BibTeX RDF	clock skew, clock gating, NBTI
4	Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang	Skew-aware polarity assignment in clock tree.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	peak current, polarity assignment, power/ground noise, Clock skew, clock tree
4	Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner	Custom topology rotary clock router with tree subnetworks.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Resonant rotary clocking, clock network design, multiphase synchronization, clock skew
4	Atanu Chattopadhyay, Zeljko Zilic	Serial reconfigurable mismatch-tolerant clock distribution.	DAC	2009	DBLP DOI BibTeX RDF	process variation, clock skew, clock networks
4	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
4	Olivier Bezet, Véronique Berge-Cherfaoui	On-line and post-processing timestamp correspondence for free-running clock nodes, using a network clock.	Real-Time Systems	2008	DBLP DOI BibTeX RDF	Timestamping conversion, Timestamping error modeling, Free running clock nodes, Network clock, Distributed architecture
4	Julien Lamoureux, Steven J. E. Wilton	On the trade-off between power and flexibility of FPGA clock networks.	TRETS	2008	DBLP DOI BibTeX RDF	clock-aware placement, FPGA, low-power design, clock distribution networks
4	Shinya Abe, Masanori Hashimoto, Takao Onoye	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution.	ISQED	2008	DBLP DOI BibTeX RDF	mesh-style clock distribution, clock skew, manufacturing variability
4	Gustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis	A novel scheme to reduce short-circuit power in mesh-based clock architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	clock mesh, power, clock skew, short-circuit
4	Heinrich Moser, Ulrich Schmid	Optimal Deterministic Remote Clock Estimation in Real-Time Systems.	OPODIS	2008	DBLP DOI BibTeX RDF	optimal clock synchronization, remote clock estimation, real-time systems, Distributed algorithms, computing models
4	Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
4	JeongKi Park, Young-Tak Kim	An Enhanced SNTP (ESNTP) Clock Synchronization for High-Precision Network QoS Measurements.	IPOM	2008	DBLP DOI BibTeX RDF	delay and jitter, clock drift compensation, QoS, performance measurement, Clock synchronization
4	Chuan Lin, Hai Zhou	Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains.	ASP-DAC	2007	DBLP DOI BibTeX RDF	delay padding, prescribed skew domains, optimal skew scheduling algorithm, domain assignment, sequential circuit, flip-flops, memory elements, clock period, clock skew scheduling
4	Malay K. Ganai, Aarti Gupta	Efficient BMC for Multi-Clock Systems with Clocked Specifications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks
4	Kursat Kursat Ozenc, James P. Brommer, Bong-keum Jeong, Nina Shih, Karen Au, John Zimmerman	Reverse alarm clock: a research through design example of designing for the self.	DPPI	2007	DBLP DOI BibTeX RDF	alarm clock, bedtime, designing for the self, material possession attachment, children, time, clock, consumer behavior, parents, social role, wakeup
4	Uri Frank, Tsachy Kapschitz, Ran Ginosar	A predictive synchronizer for periodic clock domains.	Formal Methods in System Design	2006	DBLP DOI BibTeX RDF	Predictive Synchronizer, Multiple Clock Domains (MCD), Formal Verification, Systems on Chip (SoC), Clock Synchronization, Metastability
4	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic thermal clock skew compensation using tunable delay buffers.	ISLPED	2006	DBLP DOI BibTeX RDF	temperature aware design methodology, tunable delay buffers, clock skew, clock tree
4	Cecilia Metra, Stefano Di Francescantonio, T. M. Mak	Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	clock faults, Testing, clock distribution network, manufacturing test
4	Ali Kanso	More Generalized Clock-Controlled Alternating Step Generator.	ACNS	2004	DBLP DOI BibTeX RDF	Clock-Controlled Registers, Alternating Step Generator and Clock-Controlled Alernating Step Generator, Stream Ciphers
4	Sandeep Kumar Goel, Bart Vermeulen	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
4	Chunhong Chen, Changjun Kang, Majid Sarrafzadeh	Activity-sensitive clock tree construction for low power.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, clock gating, clock tree, activity pattern
4	Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal	Worst case clock skew under power supply variations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	clock skew, power supply noise, clock network
4	Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak	Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	clock faults, testing, microprocessor, Clock distribution network
4	Mely Chen Chi, Shih-Hsu Huang	A Reliable Clock Tree Design Methodology for ASIC Designs.	ISQED	2000	DBLP DOI BibTeX RDF	Clock tree design, Clock tree synthesis
4	Mohamed Nekili, Yvon Savaria, Guy Bois	Design of Clock Distribution Networks in Presence of Process Variations.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	process variations, clock skew, clock distribution
4	Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal	Path Delay Testing: Variable-Clock Versus Rated-Clock.	VLSI Design	1998	DBLP DOI BibTeX RDF	rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test
4	Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani	Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule
4	En-Shou Chang, Daniel Gajski, Sanjiv Narayan	An optimal clock period selection method based on slack minimization criteria.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	clock slack, scheduling, performance estimation, clock period
4	Guy Even, Ami Litman	Overcoming chip-to-chip delays and clock skews.	ASAP	1996	DBLP DOI BibTeX RDF	chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
4	Conrado Daws, Sergio Yovine	Reducing the number of clock variables of timed automata. (PDF / PS)	IEEE Real-Time Systems Symposium	1996	DBLP DOI BibTeX RDF	clock variable number reduction, active clock detection, equal clock detection, memory space reduction, real-time systems, real time systems, verification, case studies, timed automata, bisimulation, experimental results, system evolution
4	Maheshwar Umasankar, Ahmed El-Amawy	Generalized Algorithms for Systematic Synthesis of Branch-and-Combine Clock Networks for Meshes, Tori, and Hypercubes.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	skew bound, Branch-and-Combine, feature cycle length, hypercube, mesh, tile, torus, Clock skew, clock network
4	Danny Dolev, Joseph Y. Halpern, Barbara Simons, H. Raymond Strong	Dynamic Fault-Tolerant Clock Synchronization.	J. ACM	1995	DBLP DOI BibTeX RDF	time-of-day clock, fault-tolerance, clock synchronization, Byzantine failures
4	Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh	Activity-driven clock design for low power circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	Gated Clock Tree, Sleep Mode, Power minimization, Clock Tree
4	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
4	Roland Mandler	A configurable adjunct for real time systems (CARTS). (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	utility programs, configurable adjunct for real time systems, rapid application code generation, generic user interfaces, processor restarts, incremental system integration, incremental system reconfiguration, file-based data, tailored functionality, CARTS postal system, optimal transfer methods, backplane I/O, network I/O, CARTS clock services, high resolution time of day clocks, high resolution mission clock, system wide clock synchronisation, real-time systems, user interfaces, architectures, shared memory, shared memory systems, application program interfaces, clocks, network operating systems, operating system kernels, CARTS, real time distributed systems, input-output programs, system services, intertask communication
4	K. Arvind	Probabilistic Clock Synchronization in Distributed Systems.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	distributedsystems, probability of invalidity, deterministicalgorithm, master-slave scheme, time transmission protocol, distributed processing, probability, synchronisation, clock synchronization, probabilistic algorithm, clock skew, synchronization messages
3	Mingoo Seok, David Blaauw, Dennis Sylvester	Clock network design for ultra-low power applications.	ISLPED	2010	DBLP DOI BibTeX RDF	ultra-low power, robust design, clock network
3	Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu	Logic synthesis for low power using clock gating and rewiring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, logic synthesis, clock gating
3	Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	Clock skew reduction by self-compensating manufacturing variability with on-chip sensors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	on-chip sensors, self-compensation, clock distribution, manufacturing variability
3	Cliff C. N. Sze	ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.	ISPD	2010	DBLP DOI BibTeX RDF	VLSI, benchmarks, physical design, clock network synthesis
3	Ying-Yu Chen, Chen Dong, Deming Chen	Clock tree synthesis under aggressive buffer insertion.	DAC	2010	DBLP DOI BibTeX RDF	slew, buffer insertion, buffer sizing, clock tree, maze routing
3	Tak-Yung Kim, Taewhan Kim	Clock tree synthesis with pre-bond testability for 3D stacked IC designs.	DAC	2010	DBLP DOI BibTeX RDF	optimization, routing, buffer insertion, 3D ICs, clock tree
3	Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis	Non-uniform clock mesh optimization with linear programming buffer insertion.	DAC	2010	DBLP DOI BibTeX RDF	clock mesh optimization, robust design
3	Hyuntae Cho, Hyunsung Jang, Yunju Baek	Multi-Phase Correlator-based Realistic Clock Synchronization for Wireless Networks on IEEE 802.15.4.	CIT	2010	DBLP DOI BibTeX RDF	multi-phase correlator, precision clock, clock synchronization
3	Fabian Kuhn, Christoph Lenzen, Thomas Locher, Rotem Oshman	Optimal gradient clock synchronization in dynamic networks.	PODC	2010	DBLP DOI BibTeX RDF	clock synchronization, dynamic networks
3	Martin Bichler, Pasha Shabalin, Georg Ziegler	Efficiency with linear prices: a theoretical and experimental analysis of the combinatorial clock auction.	ACM Conference on Electronic Commerce	2010	DBLP DOI BibTeX RDF	allocative efficiency, combinatorial clock auction, core-selecting auctions, ex-post equilibrium
3	Chrisil Arackaparambil, Sergey Bratus, Anna Shubina, David Kotz	On the reliability of wireless fingerprinting using clock skews.	WISEC	2010	DBLP DOI BibTeX RDF	fake access point, mac address spoofing, wireless, ieee 802.11, fingerprinting, clock skew, timestamp
3	Isamu Tsuneizumi, Ailixier Aikebaier, Tomoya Enokido, Makoto Takizawa	Reduction of Messages Unnecessarily Ordered in Scalable Group Communication.	CISIS	2010	DBLP DOI BibTeX RDF	physical clock, linear clock, distributed systems, P2P system, logical clock
3	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
3	Dumitru Potop-Butucaru, Robert de Simone, Yves Sorel, Jean-Pierre Talpin	Clock-driven distributed real-time implementation of endochronous synchronous programs.	EMSOFT	2009	DBLP DOI BibTeX RDF	clock calculus, distributed real-time scheduling, intermediate representation, synchronous model
3	Pei-Hsin Ho	Industrial clock design.	ISPD	2009	DBLP DOI BibTeX RDF	low power, variability, physical design, clock tree synthesis
3	Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert	Ispd2009 clock network synthesis contest.	ISPD	2009	DBLP DOI BibTeX RDF	benchmarks, physical design, vlsi, clock network synthesis
3	Rupesh S. Shelar	An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.	ISPD	2009	DBLP DOI BibTeX RDF	routing, power, clock distribution
3	Jongmin Lee, Eujoon Byun, Hanmook Park, Jongmoo Choi, Donghee Lee, Sam H. Noh	CPS-SIM: configurable and accurate clock precision solid state drive simulator.	SAC	2009	DBLP DOI BibTeX RDF	SSD (solid state drive), clock precision SSD simulator, configurability, NAND flash memory, FTL (flash translation layer)
3	Fabian Kuhn, Rotem Oshman	Gradient Clock Synchronization Using Reference Broadcasts.	OPODIS	2009	DBLP DOI BibTeX RDF	Gradient Clock Synchronization, Wireless Networks
3	Hochang Jang, Taewhan Kim	Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.	DAC	2009	DBLP DOI BibTeX RDF	clock synthesis, power/ground noise, buffer insertion
3	Sari Onaissi, Khaled R. Heloue, Farid N. Najm	Clock skew optimization via wiresizing for timing sign-off covering all process corners.	DAC	2009	DBLP DOI BibTeX RDF	clock skew optimization, parameterized timing analysis, sign-off, wiresizing, variability
3	Eli Arbel, Cindy Eisner, Oleg Rokhlenko	Resurrecting infeasible clock-gating functions.	DAC	2009	DBLP DOI BibTeX RDF	clustering, low power, approximation, clock gating
3	Anthony Rowe, Vikram Gupta, Ragunathan Rajkumar	Low-power clock synchronization using electromagnetic energy radiating from AC power lines.	SenSys	2009	DBLP DOI BibTeX RDF	hardware clock synchronization, wireless sensor networks, sensor networks, synchronization
3	Christoph Lenzen, Philipp Sommer, Roger Wattenhofer	Optimal clock synchronization in networks.	SenSys	2009	DBLP DOI BibTeX RDF	sensor networks, lower bound, time synchronization, clock drift
3	Jiang Long, Andrew Seawright, Paparao Kavalipati	Multi-clock SVA synthesis without re-writing.	ASP-DAC	2009	DBLP DOI BibTeX RDF	SVA, multi-clock SVA assertions
3	Fabian Kuhn, Thomas Locher, Rotem Oshman	Gradient clock synchronization in dynamic networks.	SPAA	2009	DBLP DOI BibTeX RDF	distributed algorithms, clock synchronization, dynamic networks
3	Faranak Heidarian, Julien Schmaltz, Frits W. Vaandrager	Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks.	FM	2009	DBLP DOI BibTeX RDF	wireless sensor networks, model checking, theorem proving, timed automata, clock synchronization, industrial application
3	Christoph Lenzen, Thomas Locher, Roger Wattenhofer	Tight bounds for clock synchronization.	PODC	2009	DBLP DOI BibTeX RDF	gradient property, optimal skew bounds, clock synchronization
3	Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Power efficient tree-based crosslinks for skew reduction.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crosslink, non-tree clock distribution network, power, mesh, skew, clock tree
3	Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu	Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.	ISQED	2008	DBLP DOI BibTeX RDF	clock mesh, dynamic time step rounding, simulation, macromodel
3	Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng	Clock Skew Analysis via Vector Fitting in Frequency Domain.	ISQED	2008	DBLP DOI BibTeX RDF	vector fitting, clock skew, frequency domain
3	Jaehan Lee, Jang-Sub Kim, Erchin Serpedin	Clock Offset Estimation in Wireless Sensor Networks Using Bootstrap Bias Correction.	WASA	2008	DBLP DOI BibTeX RDF	Bias Correction, Wireless Sensor Networks, Bootstrap, Clock Synchronization
3	Venkatesh Arunachalam, Wayne Burleson	Low-power clock distribution in a multilayer core 3d microprocessor.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	3D ic's, 3D processor architectures, clock grids
3	Rupak Samanta, Jiang Hu, Peng Li	Discrete buffer and wire sizing for link-based non-tree clock networks.	ISPD	2008	DBLP DOI BibTeX RDF	non-tree, buffer, clock, wire, svm
3	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
3	Sirio Scipioni, Leonardo Querzoni, Sara Tucci Piergiovanni, Roberto Baldoni	A theoretical evaluation of peer-to-peer internal clock synchronization.	Autonomics	2008	DBLP DOI BibTeX RDF	internal clock synchronization, peer-to-peer systems, theoretical analysis
3	Aaron P. Hurst	Automatic synthesis of clock gating logic with controlled netlist perturbation.	DAC	2008	DBLP DOI BibTeX RDF	low power, clock gating, logic optimization, dynamic power
3	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
3	Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni	Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.	DAC	2008	DBLP DOI BibTeX RDF	non-Gaussian, process variations, yield, clock skew scheduling
3	Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed	A new paradigm for synthesis and propagation of clock gating conditions.	DAC	2008	DBLP DOI BibTeX RDF	low-power design, clock gating
3	Anand Rajaram, David Z. Pan	Robust chip-level clock tree synthesis for SOC designs.	DAC	2008	DBLP DOI BibTeX RDF	chip-level CTS, physical design, clock network
3	Arun Rangasamy, Rahul Nagpal, Y. N. Srikant	Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	dvs, dynamic energy, energy, multiple clock domains
3	King Leong Lee, Nadir Z. Basturkmen, Srikanth Venkataraman	Diagnosis of Scan Clock Failures.	VTS	2008	DBLP DOI BibTeX RDF	scan clock, diagnosis, scan chain
3	N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung	Measuring and modeling FPGA clock variability.	FPGA	2008	DBLP DOI BibTeX RDF	within-die variability, modeling, FPGA, process variation, clock skew
3	Edmar Mota-Garcia, Rogelio Hasimoto-Beltran	Clock offset estimation using collaborative one-way transit time.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	clock offset estimation, one-way transit time
3	Damián Barsotti, Leonor Prensa Nieto, Alwen Tiu	Verification of clock synchronization algorithms: experiments on a combination of deductive tools.	Formal Asp. Comput.	2007	DBLP DOI BibTeX RDF	Combination of deductive tools, Verification, Theorem proving, Clock synchronization
3	Dong Zhou, Ten-Hwang Lai	An Accurate and Scalable Clock Synchronization Protocol for IEEE 802.11-Based Multihop Ad Hoc Networks.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	scalability, MANET, IEEE 802.11, clock synchronization
3	Sergey Bereg, Yuanyi Zhang	Phylogenetic Networks Based on the Molecular Clock Hypothesis.	IEEE/ACM Trans. Comput. Biology Bioinform.	2007	DBLP DOI BibTeX RDF	molecular clock hypothesis, least-squares fit, Phylogenetic Networks
3	Josef Widder, Ulrich Schmid	Booting clock synchronization in partially synchronous systems with hybrid process and link failures.	Distributed Computing	2007	DBLP DOI BibTeX RDF	Initial clock synchronization, System start-up, Hybrid failure models, Link failures, Partially synchronous systems, Fault-tolerant distributed algorithms
3	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
3	Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert	Mutually Clock-Controlled Feedback Shift Registers Provide Resistance to Algebraic Attacks.	Inscrypt	2007	DBLP DOI BibTeX RDF	stream cipher, algebraic attacks, clock-control