Search results for "clock cycles"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Byung Kook Kim, Kang G. Shin	Scalable hardware earliest-deadline-first scheduler for ATM switching networks. (PDF / PS)	IEEE Real-Time Systems Symposium	1997	DBLP DOI BibTeX RDF	scalable hardware earliest deadline first link scheduler, ATM switching networks, fast hardware solution, switching speed, minimum size EDF priority queue, variable size FIFO queues, two port memory buffer, deadline folding technique, deadline resolution, asynchronous transfer mode, real time scheduler, simulation studies, EDF scheduler, clock cycles
2	Christian Piguet, T. Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers	Low-Power Embedded Microprocessor Design.	EUROMICRO	1996	DBLP DOI BibTeX RDF	low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles
2	Hee Yong Youn, Youngsong Mun	On Multistage Interconnection Networks with Small Clock Cycles.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF
2	Stephen J. Walsh, John A. Board	Pollution control caching. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	pollution control caching, high speed processors, bandwidth mismatch, standard DRAMS, on-chip caches, miss ratio statistics, expected clock cycles per instruction, main memory latencies, PCC+VB, discrete event simulation, memory architecture, trace driven simulation, cache storage, memory performance, ANOVA, DRAM chips
1	Flavius Opritoiu, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu	A high-speed AES architecture implementation.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cryptochip, optimization, fpga, hardware, aes
1	Jirí Simsa, Satnam Singh	Designing hardware with dynamic memory abstraction.	FPGA	2010	DBLP DOI BibTeX RDF	c to gates, high-level synthesis, parallel execution, dynamic memory, bluespec
1	Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu	32-bit floating-point FPGA gaussian elimination.	FPGA	2009	DBLP DOI BibTeX RDF	fpga., floating-point, gaussian elimination
1	Yiqing Huang, Qin Liu, Satoshi Goto, Takeshi Ikenaga	Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reconfigurable architecture, h.264, vlsi
1	Daniele Paolo Scarpazza, Gregory F. Russell	High-performance regular expression scanning on the Cell/B.E. processor.	ICS	2009	DBLP DOI BibTeX RDF	multi-core, regular expressions, cell processor
1	Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng	0.5V 160-MHz 260uW all digital phase-locked loop.	DDECS	2009	DBLP DOI BibTeX RDF
1	Koji Nakano, Kensuke Kawakami, Koji Shigemoto	RSA encryption and decryption using the redundant number system on the FPGA.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Dmitrijs Zaparanuks, Milan Jovic, Matthias Hauswirth	Accuracy of performance counter measurements.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang	Buffer/flip-flop block planning for power-integrity-driven floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
1	Kaleem Fatima, Rameshwar Rao	A New Hardware Routing Accelerator for Multi-Terminal Nets.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Uwe Brinkschulte, Daniel Lohn, Mathias Pacher	Towards a Statistical Model of a Microprocessor's Throughput by Analyzing Pipeline Stalls.	SEUS	2009	DBLP DOI BibTeX RDF
1	Thomas Polzer, Thomas Handl, Andreas Steininger	A Metastability-Free Multi-synchronous Communication Scheme for SoCs.	SSS	2009	DBLP DOI BibTeX RDF
1	Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet	Fast Simulation Techniques for Design Space Exploration.	TOOLS	2009	DBLP DOI BibTeX RDF	DIPLODOCUS, TTool, Fast Simulation Techniques, UML, System-On-Chip, Design Space Exploration, System Level Modeling
1	Christian Lederer, Roland Mader, Manuel Koschuch, Johann Großschädl, Alexander Szekely, Stefan Tillich	Energy-Efficient Implementation of ECDH Key Exchange for Wireless Sensor Networks.	WISTP	2009	DBLP DOI BibTeX RDF
1	Roberto Gutierrez, Javier Valls	Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	atan(Y/X), FPGA, Wireless communication, CORDIC
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign Bit Reduction Encoding For Low Power Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Signed multiplier, Sign extension, FIR filter, Power reduction, Energy reduction, Bus encoding
1	Krutartha Patel, Sri Parameswaran	SHIELD: a software hardware design methodology for security and reliability of MPSoCs.	DAC	2008	DBLP DOI BibTeX RDF	bit flips, tensilica, architecture, multiprocessors, code injection
1	Hitoshi Oi	Hardware support for a wireless sensor network virtual machine.	MOBILWARE	2008	DBLP DOI BibTeX RDF	wireless sensor network, virtual machine, low power design, hardware support
1	Martino Sykora, Giovanni Agosta, Cristina Silvano	Dynamic configuration of application-specific implicit instructions for embedded pipelined processors.	SAC	2008	DBLP DOI BibTeX RDF	implicit issue, reconfiguration, pipelined architecture
1	Mattias V. Eriksson, Oskar Skoog, Christoph W. Kessler	Optimal vs. heuristic integrated code generation for clustered VLIW architectures.	SCOPES	2008	DBLP DOI BibTeX RDF
1	Sundar Balasubramanian, Harold W. Carter, Andrey Bogdanov, Andy Rupp, Jintai Ding	Fast multivariate signature generation in hardware: The case of rainbow.	ASAP	2008	DBLP DOI BibTeX RDF
1	Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan	RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.	ASAP	2008	DBLP DOI BibTeX RDF
1	Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong	Scheduling with integer time budgeting for low-power optimization.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Tsuyoshi Sadakata, Yusuke Matsunaga	An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n).	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Li-Che Hung, Yaw-Chung Chen	Parallel Table Lookup for Next Generation Internet.	COMPSAC	2008	DBLP DOI BibTeX RDF	parallel processing, pipeline, multi-threading, Table lookup, longest prefix matching
1	Swaroop Ghosh, Patrick Ndai, Kaushik Roy	A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.	DATE	2008	DBLP DOI BibTeX RDF
1	Hui Liu, Huawei Li, Yu Hu, Xiaowei Li	A Scan-Based Delay Test Method for Reduction of Overtesting.	DELTA	2008	DBLP DOI BibTeX RDF	overtesting, SeBoS, delay test, IR drop
1	Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue	Improved Policies for Drowsy Caches in Embedded Processors.	DELTA	2008	DBLP DOI BibTeX RDF	Low Power Cache Design, Leakage Energy, Drowsy Cache
1	Xiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoor, James F. Plusquellic	Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis.	DFT	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Koji Shigemoto, Kensuke Kawakami, Koji Nakano	Accelerating Montgomery Modulo Multiplication for Redundant Radix-64k Number System on the FPGA Using Dual-Port Block RAMs.	EUC	2008	DBLP DOI BibTeX RDF
1	Sundar Balasubramanian, Andrey Bogdanov, Andy Rupp, Jintai Ding, Harold W. Carter	Fast Multivariate Signature Generation in Hardware: The Case of Rainbow.	FCCM	2008	DBLP DOI BibTeX RDF
1	Andre Guntoro, Manfred Glesner	A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor.	FPL	2008	DBLP DOI BibTeX RDF
1	Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez	Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC.	FPL	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
1	Junfeng Fan, Ingrid Verbauwhede	Unified Digit-Serial Multiplier and Inverter in Finite Field GF(2m).	HOST	2008	DBLP DOI BibTeX RDF
1	Zhan Ma, Yao Wang	Complexity modeling of scalable video decoding.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Mahdi Shabany, Krishna Su, P. Glenn Gulak	A pipelined scalable high-throughput implementation of a near-ML K-best complex lattice decoder.	ICASSP	2008	DBLP DOI BibTeX RDF
1	J. P. Grossman, John K. Salmon, Richard C. Ho, Doug Ierardi, Brian Towles, Brannon Batson, Jochen Spengler, Stanley C. Wang, Rolf Mueller, Michael Theobald, Cliff Young, Joseph Gagliardo, Martin M. Deneroff, Ron O. Dror, David E. Shaw	Hierarchical simulation-based verification of Anton, a special-purpose parallel machine.	ICCD	2008	DBLP DOI BibTeX RDF
1	Mohammed Berhea, Chunhong Chen, Q. M. Jonathan Wu	Protocol-level performance analysis for anti-collision protocols in RFID systems.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Laurent Boher, Rodrigue Rabineau, Maryline Hélard	Analysis of CORDIC-based triangularization for MIMO MMSE filtering.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Gian-Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang	A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Yin-Tsung Hwang, Wei-Da Chen	A low complexity complex QR factorization design for signal detection in MIMO OFDM systems.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Hyejung Kim, Yongsang Kim, Hoi-Jun Yoo	A 6.3nJ/op low energy 160-bit modulo-multiplier for elliptic curve cryptography processor.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Arash Mehrabi, Mohammad Ranjbar, Omid Oliaei	Multibit incremental data converters with reduced sensitivity to mismatch.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Mahdi Shabany, P. Glenn Gulak	Scalable VLSI architecture for K-best lattice decoders.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Salah Merniz, Mohamed Benmohammed	A Scalable Proof Methodology for RISC Processor Designs: A Functional Approach.	ITNG	2008	DBLP DOI BibTeX RDF	State functions, RISC designs, Formal Verification, Functional programming, Micro-architectures
1	Eric Chun, Zeshan Chishti, T. N. Vijaykumar	Shapeshifter: Dynamically changing pipeline width and speed to address process variations.	MICRO	2008	DBLP DOI BibTeX RDF
1	Kensuke Kawakami, Koji Shigemoto, Koji Nakano	Redundant Radix-2r Number System for Accelerating Arithmetic Operations on the FPGAs.	PDCAT	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Joon-Sung Yang, Nur A. Touba	Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture.	VTS	2008	DBLP DOI BibTeX RDF	Trace Buffer Observation Window, Two-Dimensional (2-D) Compaction, Cycling Register, Silicon Debug, MISR
1	Yu Huang 0005, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li	Survey of Scan Chain Diagnosis.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	Natasa Miskov-Zivanov, Diana Marculescu	Modeling and Optimization for Soft-Error Reliability of Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He	Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Bijan Ansari, M. Anwar Hasan	High-Performance Architecture of Elliptic Curve Scalar Multiplication.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Xiang Xiao, Jaehwan John Lee	A Novel O(1) Deadlock Detection Methodology for Multiunit Resource Systems and Its Hardware Implementation for System-on-Chip.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF
1	B. Taskin, Bo Hong	Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Sourav Das, Dipanwita Roy Chowdhury	An Efficient n×nBoolean Mapping Using Additive Cellular Automata.	ACRI	2008	DBLP DOI BibTeX RDF	Additive Cellular Automata, Pseudo-Random Number Generator
1	Maciej Wielgosz, Ernest Jamro, Kazimierz Wiatr	Highly efficient structure of 64-bit exponential function implemented in FPGAs.	ARC	2008	DBLP DOI BibTeX RDF	HPRC (High Performance Reconfigurable Computing), exponent function, FPGA, elementary function
1	Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki	High-Performance Concurrent Error Detection Scheme for AES Hardware.	CHES	2008	DBLP DOI BibTeX RDF
1	Stefan Tillich, Christoph Herbst	Boosting AES Performance on a Tiny Processor Core.	CT-RSA	2008	DBLP DOI BibTeX RDF	8-bit microcontroller, AVR architecture, Advanced Encryption Standard, instruction set extensions, hardware-software codesign
1	Rostislav (Reuven) Dobkin, Ran Ginosar	Fast Universal Synchronizers.	PATMOS	2008	DBLP DOI BibTeX RDF	MCD, Synchronization, SoC
1	Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi	An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm.	Public Key Cryptography	2008	DBLP DOI BibTeX RDF	MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication
1	John D. Davis, Zhangxi Tan, Fang Yu, Lintao Zhang	Designing an Efficient Hardware Implication Accelerator for SAT Solving.	SAT	2008	DBLP DOI BibTeX RDF
1	Cheng-Yi Xiong, Jin-Wen Tian, Jian Liu	High performance word level sequential and parallel coding methods and architectures for bit plane coding.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	bit plane coding, word-level sequential, multi-word parallel, high performance
1	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Configurable Data Memory for Multimedia Processing.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	stride access, configurable, parallel memory, skewing scheme, SIMD processing
1	Jae Hyun Baek, Sung Dae Kim, Myung Hoon Sunwoo	SPOCS: Application Specific Signal Processor for OFDM Communication Systems.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	ASSP, Communications, FFT, DSP, OFDM, Application-Specific Instruction-Set Processor (ASIP), Bit manipulation
1	Reeba Korah, J. Raja Paul Perinbam	FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	pipelining, H.264, quantization, integer transform
1	Martin Boesgaard, Mette Vesterager, Erik Zenner	The Rabbit Stream Cipher.	The eSTREAM Finalists	2008	DBLP DOI BibTeX RDF	Stream cipher, coupled, non-linear, counter, fast
1	Jeff Lewis	Cryptol: specification, implementation and verification of high-grade cryptographic applications.	FMSE	2007	DBLP DOI BibTeX RDF	cryptography, specification language, certification, high assurance, symmetric key
1	Andrew Trotman, Vikram Subramanya	Sigma encoded inverted files.	CIKM	2007	DBLP DOI BibTeX RDF	compression, inverted files
1	Natasa Miskov-Zivanov, Diana Marculescu	Soft error rate analysis for sequential circuits.	DATE	2007	DBLP DOI BibTeX RDF
1	Kim Petersén, Johnny Öberg	Toward a scalable test methodology for 2D-mesh Network-on-Chips.	DATE	2007	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda	Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault-emulation, software-based testing, FPGA, path-delay
1	Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He	Efficient decoupling capacitance budgeting considering operation and process variations.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Soo Yun Hwang, Hyeong Jun Park, Kyoung Son Jhang	An implementation and performance analysis of slave-side arbitration schemes for the ML-AHB BusMatrix.	SAC	2007	DBLP DOI BibTeX RDF	arbitration scheme, multi-layer AHB BusMatrix, slave-side arbitration, system on a chip, on chip bus
1	Sudhakar Maddi, M. B. Srinivas	A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.	SBCCI	2007	DBLP DOI BibTeX RDF	sum-carry logic, RSA, ECC, reconfigurable architectures, montgomery multiplication, unified architectures
1	Dohun Kim, Jugwan Eom, Chanik Park	L4oprof: a performance-monitoring-unit-based software-profiling framework for the L4 microkernel.	Operating Systems Review	2007	DBLP DOI BibTeX RDF
1	Imran Ahmed, Tughrul Arslan	VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian	Trace Compaction using SAT-based Reachability Analysis.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Santosh Ghosh, Monjur Alam, Indranil Sengupta, Dipanwita Roy Chowdhury	A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography.	DSD	2007	DBLP DOI BibTeX RDF
1	Johann Großschädl, Stefan Tillich, Alexander Szekely	Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor.	DSD	2007	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos	An Efficient BIST Scheme for Non-Restoring Array Dividers.	DSD	2007	DBLP DOI BibTeX RDF
1	Roberto Gutierrez, Javier Valls	Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms.	FPL	2007	DBLP DOI BibTeX RDF
1	Xiang Xiao, Jaehwan John Lee	A novel O(1) parallel deadlock detection algorithm and architecture for multi-unit resource systems.	ICCD	2007	DBLP DOI BibTeX RDF
1	Yi-Chih Chao, Hui-Hsien Tsai, Yu-Hsiu Lin, Jar-Ferr Yang, Bin-Da Liu	A Novel Design for Computation of All Transforms in H.264/AVC Decoders.	ICME	2007	DBLP DOI BibTeX RDF
1	Xiaobo Yan, Tao Tang, Yu Deng, Jing Du, Xuejun Yang	Evaluation of Transcendental Functions on Imagine Architecture.	ICPP	2007	DBLP DOI BibTeX RDF
1	Nainesh Agarwal, Nikitas J. Dimopoulos	Towards Automated Power Gating of Registers using CoDeL.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Rachit Agarwal, Emanuel M. Popovici, Brendan O'Flynn, Michael E. O'Sullivan	A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Ming-Hung Chang, Zong-Xi Yang, Wei Hwang	A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Hyojin Choi, Wonchul Lee, Wonyong Sung	Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Martin Feldhofer, Johannes Wolkerstorfer	Strong Crypto for RFID Tags - A Comparison of Low-Power Hardware Implementations.	ISCAS	2007	DBLP DOI BibTeX RDF