Search results for "clock domains"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Uri Frank, Tsachy Kapschitz, Ran Ginosar	A predictive synchronizer for periodic clock domains.	Formal Methods in System Design	2006	DBLP DOI BibTeX RDF	Predictive Synchronizer, Multiple Clock Domains (MCD), Formal Verification, Systems on Chip (SoC), Clock Synchronization, Metastability
2	Arun Rangasamy, Rahul Nagpal, Y. N. Srikant	Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	dvs, dynamic energy, energy, multiple clock domains
2	Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty	Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas	A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig	Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Fast power network analysis with multiple clock domains.	ICCD	2007	DBLP DOI BibTeX RDF
2	Nevine AbouGhazaleh, Alexandre Peixoto Ferreira, Cosmin Rusu, Ruibin Xu, Frank Liberato, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Integrated CPU and l2 cache voltage scaling using machine learning.	LCTES	2007	DBLP DOI BibTeX RDF	integrated DVS policy, machine learning, power management, multiple clock domains
2	Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux	A Survey and Taxonomy of GALS Design Styles.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	globally asynchronous, locally synchronous (GALS), clock domains, pausible clocks, loosely synchronous, synchronization, asynchronous
2	Vikram Iyengar, Gary Grise, Mark Taylor	A flexible and scalable methodology for GHz-speed structural test.	DAC	2006	DBLP DOI BibTeX RDF	asynchronous clock domains, deskewer, test waveform generator, ASICs, structural test, at-speed
2	Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty	Multi-frequency wrapper design and optimization for embedded cores under average power constraints.	DAC	2005	DBLP DOI BibTeX RDF	scan control unit, wrapper design, multiple clock domains
2	Qiang Xu, Nicola Nicolici	Wrapper Design for Testing IP Cores with Multiple Clock Domains.	DATE	2004	DBLP DOI BibTeX RDF
2	Joep L. W. Kessels, Ad M. G. Peeters, Suk-Jin Kim	Bridging Clock Domains by Synchronizing the Mice in the Mousetrap.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Ajanta Chakraborty, Mark R. Greenstreet	Efficient Self-Timed Interfaces for Crossing Clock Domains.	ASYNC	2003	DBLP DOI BibTeX RDF
2	Sandeep Kumar Goel, Bart Vermeulen	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
2	Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott	Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.	HPCA	2002	DBLP DOI BibTeX RDF	Off-Line Analysis Tool, Dynamic Reconfiguration Algorithm, Low Power, Dynamic Voltage and Frequency Scaling, Multiple Clock Domain
2	Alvin R. Albrecht, Alan J. Hu	Register Transformations with Multiple Clock Domains.	CHARME	2001	DBLP DOI BibTeX RDF
2	Robert Gage, Ben Brown	The CAT-exact data transfer to DDS-generated clock domains in a single-chip modular solution.	ITC	1998	DBLP DOI BibTeX RDF
1	Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu	Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Skew variability in 3-D ICs with multiple clock domains.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang	Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone	Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Hyunbean Yi, Sandip Kundu, Sangwook Cho, Sungju Park	A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab	Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.	ITC	2010	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Doris Chen, Deshanand Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	mtbf, fpga, metastability
1	Adam Flynn, Ann Gordon-Ross, Alan D. George	Bitstream relocation with local clock domains for partially reconfigurable FPGAs.	DATE	2009	DBLP BibTeX RDF
1	Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser	Multiple clock and voltage domains for chip multi processors.	MICRO	2009	DBLP DOI BibTeX RDF	clock domains, voltage domain, power management, DVFS, chip multi processor
1	Atanu Chattopadhyay, Zeljko Zilic	Serial reconfigurable mismatch-tolerant clock distribution.	DAC	2009	DBLP DOI BibTeX RDF	process variation, clock skew, clock networks
1	Avinash Malik, Zoran A. Salcic, Partha S. Roop	SystemJ compilation using the tandem virtual machine approach.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	SystemJ, compilation, virtual machines, System-level design, esterel
1	Kenji R. Yamamoto, Paul G. Flikkema	Prospector: Multiscale Energy Measurement of Networked Embedded Systems with Wideband Power Signals.	CSE	2009	DBLP DOI BibTeX RDF
1	Ümit Y. Ogras, Radu Marculescu, Diana Marculescu	Variation-adaptive feedback control for networks-on-chip with multiple clock domains.	DAC	2008	DBLP DOI BibTeX RDF	dynamic voltage-frequency scaling, voltage-frequency island, networks-on-chip, MPSoC, feedback control, parameter variation
1	Michal Karczmarek, Arvind	Synthesis from multi-cycle atomic actions as a solution to the timing closure problem.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li	A Case Study on At-Speed Testing for a Gigahertz Microprocessor.	DELTA	2008	DBLP DOI BibTeX RDF	test power consumption, test coverage, at-speed testing, test time, test data volume
1	Qifei Fan, Ge Zhang, Weiwu Hu	A synchronized variable frequency clock scheme in chip multiprocessors.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Integrated CPU Cache Power Management in Multiple Clock Domain Processors.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar	Fast Universal Synchronizers.	PATMOS	2008	DBLP DOI BibTeX RDF	MCD, Synchronization, SoC
1	Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy	Low-Power Hierarchical Scan Test for Multiple Clock Domains.	J. Low Power Electronics	2007	DBLP DOI BibTeX RDF
1	Yi Feng 0003, Zheng Zhou, Dong Tong, Xu Cheng	Clock domain crossing fault model and coverage metric for validation of SoC design.	DATE	2007	DBLP DOI BibTeX RDF
1	Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid	Clock-frequency assignment for multiple clock domain systems-on-a-chip.	DATE	2007	DBLP DOI BibTeX RDF
1	Rishiyur S. Nikhil	Composable Guarded Atomic Actions: a Bridging Model for SoC Design.	ACSD	2007	DBLP DOI BibTeX RDF
1	Wade L. Williams, Philip E. Madrid, Scott C. Johnson	Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Xiaowen Li, Xinkai Chen, Xiang Xie, Guolin Li, Li Zhang, Chun Zhang, Zhihua Wang	A Low Power, Fully Pipelined JPEG-LS Encoder for Lossless Image Compression.	ICME	2007	DBLP DOI BibTeX RDF
1	Atanu Chattopadhyay, Zeljko Zilic	Reconfigurable Clock Distribution Circuitry.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani	GALS Based Shared Test Architecture for Embedded Memories.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Syed Rafay Hasan, Yvon Savaria	Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu	Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji	Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara	Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.	VTS	2007	DBLP DOI BibTeX RDF	multi-clock domain, wrapper design, SoC, test scheduling, embedded core test
1	Kwang-Ting (Tim) Cheng	Combining synchronous and asynchronous timing schemes for high-performance systems.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	high-performance systems, synchronous, asynchronous, DAC, ITC
1	Hyunbean Yi, Jaehoon Song, Sungju Park	Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains.	ITC	2006	DBLP DOI BibTeX RDF
1	E. Czeck, Ravi Nanavati, Joseph E. Stoy	Reliable design with multiple clock domains.	MEMOCODE	2006	DBLP DOI BibTeX RDF
1	Suresh Balasubramanian, Narayanan Natarajan, Olivier Franza, Chris Gianos	Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Julien Lamoureux, Steven J. E. Wilton	FPGA clock network architecture: flexibility vs. area and power.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, architecture, low-power, clock network
1	Geoffrey M. Brown	Verification of a Data Synchronization Circuit For All Time.	ACSD	2006	DBLP DOI BibTeX RDF
1	Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha	An Efficient Clocking Scheme for On-Chip Communications.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng	Off-Line Testing of Delay Faults in NoC Interconnects.	DSD	2006	DBLP DOI BibTeX RDF
1	Zhonghai Lu, Ingo Sander, Axel Jantsch	Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.	DSD	2006	DBLP DOI BibTeX RDF
1	Ami Castonguay, Yvon Savaria	Architecture of a hypertransport tunnel.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Zhiyi Yu, Bevan M. Baas	Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Erno Salminen, Tero Kangas, Timo D. Hämäläinen, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna	HIBI Communication Network for System-on-Chip.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	hierarchical bus, system-on-chip, network-on-chip, wrapper
1	Mike Hutton, David Karchmer, Bryan Archell, Jason Govig	Efficient static timing analysis and applications using edge masks.	FPGA	2005	DBLP DOI BibTeX RDF	cut-path, multicycle, thru-x, FPGA, placement, timing analysis
1	Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar	An Asynchronous Router for Multiple Service Levels Networks on Chip.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.	DATE	2005	DBLP DOI BibTeX RDF
1	Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid	The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application.	DATE	2005	DBLP DOI BibTeX RDF
1	Ambar A. Gadkari, S. Ramesh	Automated Synthesis of Assertion Monitors using Visual Specifications.	DATE	2005	DBLP DOI BibTeX RDF
1	Silvio Dragone, Clemens Lombriser	The Ordering of Events in a Prototyping Platform.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Qiang Xu, Nicola Nicolici	Wrapper design for multifrequency IP cores.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Tsachy Kapschitz, Ran Ginosar	Formal Verification of Synchronizers.	CHARME	2005	DBLP DOI BibTeX RDF
1	Uri Frank, Ran Ginosar	A Predictive Synchronizer for Periodic Clock Domains.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Kees A. Vissers	Programming models and architectures for FPGA platforms.	CASES	2004	DBLP DOI BibTeX RDF
1	Jeremy W. Sheaffer, David P. Luebke, Kevin Skadron	A flexible simulation framework for graphics architectures.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
1	Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji	CESC: a visual formalism for specification and verification of SoCs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	verification, specification, visual languages, system-level design
1	César Augusto Dueñas M.	Verification and test challenges in SoC designs.	SBCCI	2004	DBLP DOI BibTeX RDF
1	Juan C. Diaz, Marta Saburit	Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit.	DATE	2004	DBLP DOI BibTeX RDF
1	Ivan Blunno, Guy Alain Narboni, Claudio Passerone	An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design.	DSD	2004	DBLP DOI BibTeX RDF
1	Yau Chin, John Sheu, David Brooks	Evaluating Techniques for Exploiting Instruction Slack.	ICCD	2004	DBLP DOI BibTeX RDF
1	YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi	The Energy Impact of Aggressive Loop Fusion.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	K. Nikila, Rubin A. Parekhji	DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device.	ITC	2004	DBLP DOI BibTeX RDF
1	Manan Syal, Michael S. Hsiao, Sreejit Chakravarty	Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.	ITC	2004	DBLP DOI BibTeX RDF
1	Mark Litterick, Joachim Geishauser	Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments.	MTV	2004	DBLP DOI BibTeX RDF
1	Giacinto Paolo Saggese, Claudio Basile, Luigi Romano, Zbigniew Kalbarczyk, Ravishankar K. Iyer	Hardware Support for High Performance, Intrusion- and Fault-Tolerant Systems.	SRDS	2004	DBLP DOI BibTeX RDF
1	Subrangshu Das, Subash G. Chandar, Ashutosh Tiwari	Reset Careabouts in a SoC Design.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Rajeev Murgai	Net Buffering in the Presence of Multiple Timing Views.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Andrew Lines	Asynchronous Interconnect for Synchronous SoC Design.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen	HIBI v.2 Communication Network for System-on-Chip.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Kees A. Vissers	Programming Extremely Flexible Platforms.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Stephan Held, Bernhard Korte, Jens Maßberg, Matthias Ringe, Jens Vygen	Clock Scheduling and Clocktree Construction for High Performance ASICS.	ICCAD	2003	DBLP DOI BibTeX RDF	ASIC
1	William S. Coates, Robert J. Drost	Congestion and Starvation Detection in Ripple FIFOs.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Ran Ginosar	Fourteen Ways to Fool Your Synchronizer.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Yaron Semiat, Ran Ginosar	Timing Measurements of Synchronization Circuits.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns	Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.	ICCD	2003	DBLP DOI BibTeX RDF
1	Edmund M. Clarke, Daniel Kroening, Karen Yorav	Specifying and Verifying Systems with Multiple Clocks.	ICCD	2003	DBLP DOI BibTeX RDF
1	Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho	Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli	High-Frequency, At-Speed Scan Testing.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas, Michael L. Scott	Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Soha Hassoun, Charles J. Alpert	Optimal path routing in single- and multiple-clock domain systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Xiaohua Kong, Radu Negulescu, Larry Weidong Ying	Refinement-based formal verification with heterogeneous timing.	STTT	2003	DBLP DOI BibTeX RDF	Communication refinement, Refinement-based verification, Relative timing, globally asynchronous locally synchronous, Process space
1	Soha Hassoun, Charles J. Alpert, Meera Thiagarajan	Optimal buffered routing path constructions for single and multiple clock domain systems.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Anoop Iyer, Diana Marculescu	Power efficiency of voltage scaling in multiple clock, multiple voltage cores.	ICCAD	2002	DBLP DOI BibTeX RDF
1	George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson	Point to Point GALS Interconnect.	ASYNC	2002	DBLP DOI BibTeX RDF