Search results for "clock gating"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Martin Saint-Laurent, Animesh Datta	A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.	ISLPED	2010	DBLP DOI BibTeX RDF	clock gater, clock gating cell, local clock buffer, set-reset latch
3	Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu	Logic synthesis for low power using clock gating and rewiring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, logic synthesis, clock gating
3	Eli Arbel, Cindy Eisner, Oleg Rokhlenko	Resurrecting infeasible clock-gating functions.	DAC	2009	DBLP DOI BibTeX RDF	clustering, low power, approximation, clock gating
3	Aaron P. Hurst	Automatic synthesis of clock gating logic with controlled netlist perturbation.	DAC	2008	DBLP DOI BibTeX RDF	low power, clock gating, logic optimization, dynamic power
3	Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed	A new paradigm for synthesis and propagation of clock gating conditions.	DAC	2008	DBLP DOI BibTeX RDF	low-power design, clock gating
3	Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron	Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices.	ISLPED	2005	DBLP DOI BibTeX RDF	architecture, power, temperature, clock gating
3	Hans M. Jacobson	Improved clock-gating through transparent pipelining.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating
2	Jens Brandt, Klaus Schneider, Sumit Ahuja, Sandeep K. Shukla	The Model Checking View to Clock Gating and Operand Isolation.	ACSD	2010	DBLP DOI BibTeX RDF	operand isolation, model checking, clock gating
2	Ashutosh Chakraborty, David Z. Pan	Skew management of NBTI impacted gated clock trees.	ISPD	2010	DBLP DOI BibTeX RDF	clock skew, clock gating, NBTI
2	Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao	Clock gating effectiveness metrics: Applications to power optimization.	ISQED	2009	DBLP DOI BibTeX RDF
2	Eli Arbel, Oleg Rokhlenko, Karen Yorav	SAT-based synthesis of clock gating functions using 3-valued abstraction.	FMCAD	2009	DBLP DOI BibTeX RDF
2	Li Li, Ken Choi, Seongmo Park, MooKyung Chung	Selective clock gating by using wasting toggle rate.	EIT	2009	DBLP DOI BibTeX RDF
2	Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou	Improve clock gating through power-optimal enable function selection.	DDECS	2009	DBLP DOI BibTeX RDF
2	Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng	Predicting the worst-case voltage violation in a 3D power network.	SLIP	2009	DBLP DOI BibTeX RDF	worst case violation prediction, integer linear programming, leakage, clock gating, power networks
2	Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen	Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power, ASIP, ECG, Clock gating, Wireless sensor node
2	Enrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino	Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.	DSD	2008	DBLP DOI BibTeX RDF
2	Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
2	Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang	A novel sequential circuit optimization with clock gating logic.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
2	Nainesh Agarwal, Nikitas J. Dimopoulos	DSPstone Benchmark of CoDeL's Automated Clock Gating Platform.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Vishwanadh Tirumalashetty, Hamid Mahmoodi	Clock Gating and Negative Edge Triggering for Energy Recovery Clock.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimin Zhang, Jun Wang	Adaptive Clock Gating Technique for Low Power IP Core in SoC Design.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
2	Yan Luo, Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan	Conserving network processor power consumption by exploiting traffic variability.	TACO	2007	DBLP DOI BibTeX RDF	scheduling, low power, Network processor, clock gating
2	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
2	Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai	Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Nainesh Agarwal, Nikitas J. Dimopoulos	Efficient Automated Clock Gating Using CoDeL.	SAMOS	2006	DBLP DOI BibTeX RDF
2	Yan Zhang, Jussi Roivainen, Aarne Mämmelä	Clock-Gating in FPGAs: A Novel and Comparative Evaluation.	DSD	2006	DBLP DOI BibTeX RDF
2	Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia	Low power synthesis of dynamic logic circuits using fine-grained clock gating.	DATE	2006	DBLP DOI BibTeX RDF
2	Nainesh Agarwal, Nikitas J. Dimopoulos	Power efficient rapid hardware development using CoDel and automated clock gating.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel	Power-Clock Gating in Adiabatic Logic Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.	HPCA	2005	DBLP DOI BibTeX RDF
2	Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin	Speculative software management of datapath-width for energy optimization.	LCTES	2004	DBLP DOI BibTeX RDF	narrow-width regions, compiler, reconfigurable computing, speculative execution, energy management, clock-gating
2	Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii	Clock-tree power optimization based on RTL clock-gating.	DAC	2003	DBLP DOI BibTeX RDF	clock-tree synthsis, low-power design
2	Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy	Deterministic Clock Gating for Microprocessor Power Reduction.	HPCA	2003	DBLP DOI BibTeX RDF
2	Juanjo Noguera, Rosa M. Badia	System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures.	CASES	2003	DBLP DOI BibTeX RDF	reconfigurable computing, dynamic scheduling, clock-gating, frequency scaling, power-performance trade-offs
2	Pilar Parra, Antonio J. Acosta, Manuel Valencia	Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Chunhong Chen, Changjun Kang, Majid Sarrafzadeh	Activity-sensitive clock tree construction for low power.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, clock gating, clock tree, activity pattern
2	Wael El-Essawy, David H. Albonesi, Balaram Sinharoy	A microarchitectural-level step-power analysis tool.	ISLPED	2002	DBLP DOI BibTeX RDF	Ldi/dt, step-power, microprocessors, clock-gating, architectural simulation, inductive noise
2	Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster	Synchronous Interlocked Pipelines.	ASYNC	2002	DBLP BibTeX RDF	progressive stalls, synchronous, Pipeline, asynchronous, clock gating, elastic, interlocked
2	David Brooks, Margaret Martonosi	Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance.	ACM Trans. Comput. Syst.	2000	DBLP DOI BibTeX RDF
2	Xunwei Wu, Massoud Pedram	Low power sequential circuit design by using priority encoding and clock gating.	ISLPED	2000	DBLP DOI BibTeX RDF
2	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang	Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
1	Li Li, Ken Choi, Haiqing Nan	Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously.	ISQED	2011	DBLP DOI BibTeX RDF
1	Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen	Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing.	ITC	2011	DBLP DOI BibTeX RDF
1	Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy	Low power compression utilizing clock-gating.	ITC	2011	DBLP DOI BibTeX RDF
1	Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino	Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki	Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Ting-Hao Lin, Chung-Yang (Ric) Huang	Using SAT-based Craig interpolation to enlarge clock gating functions.	DAC	2011	DBLP DOI BibTeX RDF
1	Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin	Pulser gating: A clock gating of pulsed-latch circuits.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu	On applying erroneous clock gating conditions to further cut down power.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick	Structural tests of slave clock gating in low-power flip-flop.	VTS	2011	DBLP DOI BibTeX RDF
1	Luca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar	A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.	DATE	2011	DBLP DOI BibTeX RDF
1	Shih-Jung Hsu, Rung-Bin Lin	Clock gating optimization with delay-matching.	DATE	2011	DBLP BibTeX RDF
1	Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu	A clock-gating based capture power droop reduction methodology for at-speed scan testing.	DATE	2011	DBLP BibTeX RDF
1	Luca Benini, Alberto Bocca, Alberto Bonanno, Alberto Macii, Enrico Macii, Jean-Luc Nagel, Christian Piguet, Massimo Poncino	A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Xin Man, Takashi Horiyama, Shinji Kimura	Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Wing-Shan Tam, Oi-Ying Wong, Ka-Yan Mok, Chi-Wah Kok, Hei Wong	An Energy Efficient Half-Static Clock-Gating d-Type flip-Flop.	Journal of Circuits, Systems, and Computers	2010	DBLP DOI BibTeX RDF
1	Antonin Hermanek, Michal Kunes, Milan Tichý	Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique.	FPL	2010	DBLP DOI BibTeX RDF
1	Sumit Ahuja, Wei Zhang, Sandeep K. Shukla	System level simulation guided approach to improve the efficacy of clock-gating.	HLDVT	2010	DBLP DOI BibTeX RDF
1	Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan	Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy	Improved clock-gating control scheme for transparent pipeline.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jithendra Srinivas, Sukumar Jairam	Clock gating approaches by IOEX graphs and cluster efficiency plots.	DATE	2010	DBLP BibTeX RDF
1	Javier Castro, Pilar Parra, Antonio J. Acosta	Optimization of clock-gating structures for low-leakage high-performance applications.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla	A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms.	VLSI Design	2010	DBLP DOI BibTeX RDF	C2R, Hardware Coprocessor, Software Algorithms, High Level Synthesis, Clock-gating, Power Reduction
1	Jun Seomun, Insup Shin, Youngsoo Shin	Synthesis and implementation of active mode power gating circuits.	DAC	2010	DBLP DOI BibTeX RDF	active leakage, active-mode power gating, low power
1	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
1	Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao, Nam Sung Kim	Workload-adaptive process tuning strategy for power-efficient multi-core processors.	ISLPED	2010	DBLP DOI BibTeX RDF	process parameter tuning, DVFS, multi-core processor
1	Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Efficient Power Network Analysis Considering Multidomain Clock Gating.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy	Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Young-Won Kim, Joo-Seong Kim, Jae-Hyuk Oh, Yoon-Suk Park, Jong-Woo Kim, Kwang-Il Park, Bai-Sun Kong, Young-Hyun Jun	Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang	Capture power reduction using clock gating aware test generation.	ITC	2009	DBLP DOI BibTeX RDF
1	Safeen Huda, Muntasir Mallick, Jason Helge Anderson	Clock gating architectures for FPGA power reduction.	FPL	2009	DBLP DOI BibTeX RDF
1	Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino	Data-Driven Clock Gating for Digital Filters.	PATMOS	2009	DBLP DOI BibTeX RDF
1	S. Ahuja, S. Shukla	MCBCG: Model Checking Based Sequential Clock-Gating.	HLDVT	2009	DBLP DOI BibTeX RDF
1	Nasir Mohyuddin, Kimish Patel, Massoud Pedram	Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors.	ICCD	2009	DBLP DOI BibTeX RDF
1	Andrew Herdrich, Ramesh Illikkal, Ravi R. Iyer, Donald Newell, Vineet Chadha, Jaideep Moses	Rate-based QoS techniques for cache/memory in CMP platforms.	ICS	2009	DBLP DOI BibTeX RDF	p-states, performance differentiation, t-states, cache, memory, rate control, qos, clock gating, frequency scaling, dvfs
1	P. Subramanian, Jagonda Patil, Manish Kumar Saxena	FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications.	IWCMC	2009	DBLP DOI BibTeX RDF	ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
1	Ramkumar Jayaseelan, Tulika Mitra	Dynamic thermal management via architectural adaptation.	DAC	2009	DBLP DOI BibTeX RDF	architecture adaptation, dynamic thermal management
1	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
1	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
1	Massoud Pedram	Green computing: reducing energy cost and carbon footprint of information processing systems.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	power and thermal management, energy efficiency, data center, green computing
1	Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim, Hoi-Jun Yoo	A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management.	ISLPED	2009	DBLP DOI BibTeX RDF	energy efficient object recognition, multimedia processor, workload-aware dynamic power management
1	Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic	Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing.	ASAP	2009	DBLP DOI BibTeX RDF
1	Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz	MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.	DDECS	2009	DBLP DOI BibTeX RDF
1	Babak Hidaji, Mohamad Reza Andalibizadeh, Salar Alipour	Micro-architectural power estimation and optimization.	EIT	2009	DBLP DOI BibTeX RDF
1	Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi	CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.	HPCA	2009	DBLP DOI BibTeX RDF
1	Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero	Clock gate on abort: Towards energy-efficient hardware Transactional Memory.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi	Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.	SAMOS	2009	DBLP DOI BibTeX RDF
1	William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer	Reconfigurable design with clock gating.	ICSAMOS	2008	DBLP DOI BibTeX RDF
1	Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao	Clock gating for power optimization in ASIC design cycle theory & practice.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
1	Andreas Merkel, Frank Bellosa	Task activity vectors: a new metric for temperature-aware scheduling.	EuroSys	2008	DBLP DOI BibTeX RDF	activity vectorsvectors, hotspot reduction, task characteristics, temperature-aware scheduling, thermal management, task migration
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
1	Heng Liu, Yan Wang	An Implementation Scheme of Power Saving Mechanism for IEEE 802.11e.	CSSE	2008	DBLP DOI BibTeX RDF
1	Xunying Zhang, Xubang Shen	A Power-Efficient Floating-Point Co-processor Design.	CSSE	2008	DBLP DOI BibTeX RDF
1	Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng	Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.	DATE	2008	DBLP DOI BibTeX RDF