Search results for "clock network"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Mingoo Seok, David Blaauw, Dennis Sylvester	Clock network design for ultra-low power applications.	ISLPED	2010	DBLP DOI BibTeX RDF	ultra-low power, robust design, clock network
3	Cliff C. N. Sze	ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.	ISPD	2010	DBLP DOI BibTeX RDF	VLSI, benchmarks, physical design, clock network synthesis
3	Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert	Ispd2009 clock network synthesis contest.	ISPD	2009	DBLP DOI BibTeX RDF	benchmarks, physical design, vlsi, clock network synthesis
3	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
3	Julien Lamoureux, Steven J. E. Wilton	FPGA clock network architecture: flexibility vs. area and power.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, architecture, low-power, clock network
3	Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Navigating registers in placement for clock network minimization.	DAC	2005	DBLP DOI BibTeX RDF	low power, placement, clock network, variation tolerance
3	Jindrich Zejda, Paul Frain	General framework for removal of clock network pessimism.	ICCAD	2002	DBLP DOI BibTeX RDF	clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron
2	Hai Wang, Hao Yu, Sheldon X.-D. Tan	Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
2	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
2	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
2	Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska	General skew constrained clock network sizing based on sequential linear programming.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu	Clock network minimization methodology based on incremental placement.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Anand Rajaram, David Z. Pan, Jiang Hu	Improved algorithms for link-based non-tree clock networks for skew variability reduction.	ISPD	2005	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
2	Kai Wang, Malgorzata Marek-Sadowska	Clock network sizing via sequential linear programming with time-domain analysis.	ISPD	2004	DBLP DOI BibTeX RDF	sequential linear programming, sizing, clock skew, time-domain analysis
2	Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan	A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.	ICCD	2004	DBLP DOI BibTeX RDF
2	Anand Rajaram, Jiang Hu, Rabi N. Mahapatra	Reducing clock skew variability via cross links.	DAC	2004	DBLP DOI BibTeX RDF	VLSI, physical design, variation, clock network synthesis
2	Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal	Worst case clock skew under power supply variations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	clock skew, power supply noise, clock network
2	Qing Zhu, Wayne Wei-Ming Dai	High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham	A new clock network synthesizer for modern VLSI designs.	Integration	2012	DBLP DOI BibTeX RDF
1	Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young	Crosslink insertion for variation-driven clock network construction.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov	Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	systems on chips, physical synthesis
1	Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho	An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim	Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits.	ISLPED	2011	DBLP BibTeX RDF
1	Tarun Mittal, Cheng-Kok Koh	Cross link insertion for improving tolerance to variations in clock network synthesis.	ISPD	2011	DBLP DOI BibTeX RDF
1	Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang	Fault-tolerant 3D clock network.	DAC	2011	DBLP DOI BibTeX RDF
1	Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu	PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze	The future of clock network synthesis.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Vijayalakshmi Srinivasan	Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian	A low power clock network placement framework.	ISQED	2010	DBLP DOI BibTeX RDF
1	Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham	Clock Network Synthesis with Concurrent Gate Insertion.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young	A dual-MST approach for clock network synthesis.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Xin Zhao, Sung Kyu Lim	Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Liang Yang, Bao-Xia Fan, Ming Cong, Ji-Ye Zhao	Register relocation to optimize clock network for multi-domain clock skew scheduling.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Anton Korniienko, Éric Colinet, Gérard Scorletti, Eric Blanco, Dimitri Galayko, Jérôme Juillard	A clock network of distributed ADPLLs using an asymmetric comparison strategy.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young	Local clock skew minimization using blockage-aware mixed tree-mesh clock network.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li	Accurate clock mesh sizing via sequential quadraticprogramming.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, sequential quadratic programming
1	Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner	Custom topology rotary clock router with tree subnetworks.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Resonant rotary clocking, clock network design, multiphase synchronization, clock skew
1	Shota Ishihara, Masanori Hariyama, Michitaka Kameyama	A low-power FPGA based on autonomous fine-grain power-gating.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Atanu Chattopadhyay, Zeljko Zilic	Serial reconfigurable mismatch-tolerant clock distribution.	DAC	2009	DBLP DOI BibTeX RDF	process variation, clock skew, clock networks
1	Sari Onaissi, Khaled R. Heloue, Farid N. Najm	Clock skew optimization via wiresizing for timing sign-off covering all process corners.	DAC	2009	DBLP DOI BibTeX RDF	clock skew optimization, parameterized timing analysis, sign-off, wiresizing, variability
1	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
1	Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Power efficient tree-based crosslinks for skew reduction.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crosslink, non-tree clock distribution network, power, mesh, skew, clock tree
1	Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang	Skew-aware polarity assignment in clock tree.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	peak current, polarity assignment, power/ground noise, Clock skew, clock tree
1	Eli Arbel, Oleg Rokhlenko, Karen Yorav	SAT-based synthesis of clock gating functions using 3-valued abstraction.	FMCAD	2009	DBLP DOI BibTeX RDF
1	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.	ISQED	2009	DBLP DOI BibTeX RDF
1	Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi	SEU hardened clock regeneration circuits.	ISQED	2009	DBLP DOI BibTeX RDF
1	Sobeeh Almukhaizim, Ozgur Sinanoglu	Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
1	Gunok Jung, Chunghee Kim, Kyoungkuk Chae, Gi-Ho Park, Sung-Bae Park	Power and Skew Aware Point Diffusion Clock Network.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong	Leakage power optimization for clock network using dual-Vth technology.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
1	Anand Rajaram, David Z. Pan	Robust chip-level clock tree synthesis for SOC designs.	DAC	2008	DBLP DOI BibTeX RDF	chip-level CTS, physical design, clock network
1	Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed	A new paradigm for synthesis and propagation of clock gating conditions.	DAC	2008	DBLP DOI BibTeX RDF	low-power design, clock gating
1	Yesin Ryu, Taewhan Kim	Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Rupak Samanta, Jiang Hu, Peng Li	Discrete buffer and wire sizing for link-based non-tree clock networks.	ISPD	2008	DBLP DOI BibTeX RDF	non-tree, buffer, clock, wire, svm
1	Julien Lamoureux, Steven J. E. Wilton	On the trade-off between power and flexibility of FPGA clock networks.	TRETS	2008	DBLP DOI BibTeX RDF	clock-aware placement, FPGA, low-power design, clock distribution networks
1	Satish Sivaswamy, Kia Bazargan	Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs.	TRETS	2008	DBLP DOI BibTeX RDF	skew assignment, routing, Statistical timing analysis
1	Ruiming Chen, Lizheng Zhang, Vladimir Zolotov, Chandu Visweswariah, Jinjun Xiong	Static timing: Back to our roots.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Saihua Lin, Yu Wang 0002, Rong Luo, Huazhong Yang	A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian	Low power clock buffer planning methodology in F-D placement for large scale circuit design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi	An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty.	DSD	2008	DBLP DOI BibTeX RDF
1	Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao	X-clock routing based on pattern matching.	SoCC	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan	Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.	ISQED	2007	DBLP DOI BibTeX RDF
1	Xinjie Wei, Yici Cai, Xianlong Hong	Physical aware clock skew rescheduling.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	skew rescheduling, process variations, clock skew
1	Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang	Skew aware polarity assignment in clock tree.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman	A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Zhengtao Yu 0002, Xun Liu	Design of Rotary Clock Based Circuits.	DAC	2007	DBLP DOI BibTeX RDF
1	Julien Lamoureux, Steven J. E. Wilton	Clock-Aware Placement for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
1	Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino	Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai	Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Ashok Narasimhan, Ramalingam Sridhar	Impact of Variability on Clock Skew in H-tree Clock Networks.	ISQED	2007	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
1	Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama Mohan	An ECO Technique for Removing Crosstalk Violations in Clock Networks.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Jiang Hu	A Placement Methodology for Robust Clocking.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Jiang Hu, Frank Liu	Integrated Placement and Skew Optimization for Rotary Clocking.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Evaluation of a Low-Power Clock Distribution Network Based on EPIC.	NPC	2007	DBLP DOI BibTeX RDF
1	Min-Seok Kim, Jiang Hu	Associative skew clock routing for difficult instances.	DATE	2006	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze	Integrated placement and skew optimization for rotary clocking.	DATE	2006	DBLP DOI BibTeX RDF
1	Rupak Samanta, Ganesh Venkataraman, Jiang Hu	Clock buffer polarity assignment for power noise reduction.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic thermal clock skew compensation using tunable delay buffers.	ISLPED	2006	DBLP DOI BibTeX RDF	temperature aware design methodology, tunable delay buffers, clock skew, clock tree
1	Arjun Rajagopal	Clock tree design challenges for robust and low power design.	ISPD	2006	DBLP DOI BibTeX RDF	NBTI, IR drop
1	José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López	Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.	DSD	2006	DBLP DOI BibTeX RDF
1	Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen	Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA.	DSD	2006	DBLP DOI BibTeX RDF
1	Julien Lamoureux, Steven J. E. Wilton	Architecture and CAD for FPGA Clock Networks.	FPL	2006	DBLP DOI BibTeX RDF
1	Suryanarayana Tatapudi, José G. Delgado-Frias	A mesochronous pipeline scheme for high performance low power digital systems.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria	Zero skew differential clock distribution network.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Zhuo Feng, Peng Li, Jiang Hu	Efficient Model Update for General Link-Insertion Networks.	ISQED	2006	DBLP DOI BibTeX RDF
1	Xinjie Wei, Yici Cai, Xianlong Hong	Clock Skew Scheduling Under Process Variations.	ISQED	2006	DBLP DOI BibTeX RDF
1	Anand Rajaram, Jiang Hu, Rabi N. Mahapatra	Reducing clock skew variability via crosslinks.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll	Hybrid Functional and Instruction Level Power Modeling for Embedded Processors.	SAMOS	2006	DBLP DOI BibTeX RDF
1	Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan	A Fast Delay Computation for the Hybrid Structured Clock Network.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Chin-Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Navigating Register Placement for Low Power Clock Network Design.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Register placement for low power clock network.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen	Statistical based link insertion for robust clock network design.	ICCAD	2005	DBLP BibTeX RDF
1	Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu	Minimizing peak current via opposite-phase clock tree.	DAC	2005	DBLP DOI BibTeX RDF	low power, physical design, clock network synthesis
1	Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu	Skew scheduling and clock routing for improved tolerance to process variations.	ASP-DAC	2005	DBLP DOI BibTeX RDF	layout embedding, skew scheduling, reliability, process variation, clock routing
1	Yan Luo, Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan	Low power network processor design using clock gating.	DAC	2005	DBLP DOI BibTeX RDF	low power, network processors