Search results for "clock recovery"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Shuai Zhu, Yuanxin Xu, Jie Zhang, Yang Wang	The Study and Analysis of Joint Adaptive Clock Recovery Mechanism for TDMoIP.	ICNSC	2008	DBLP DOI BibTeX RDF
2	Pyung-Su Han, Woo-Young Choi	1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18µm CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Jiawen Hu	A clock recovery circuit for blind equalization multi-Gbps serial data links.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Hyoungsoo Kim, Youngsik Hur, Moonkyun Maeng, Franklin Bien, Soumya Chandramouli, Edward Gebara, Joy Laskar	A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling.	IWSOC	2005	DBLP DOI BibTeX RDF
2	Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici	Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.	DATE	2005	DBLP DOI BibTeX RDF
2	Wen Tsern Ho, Mourad N. El-Gamal	Fully-differential 13 Gbps clock recovery circuit for OC-255 SONET applications.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Faisal A. Musa, Anthony Chan Carusone	Clock recovery in high-speed multilevel serial links.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Marco Balsi, Francesco Centurelli, Giuseppe Scotti, P. Tommasino, Alessandro Trifiletti	An accurate behavioral model of phase detectors for clock recovery circuits.	ISCAS	2003	DBLP DOI BibTeX RDF
2	W. K. Yeung, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun	Clock recovery circuit with adiabatic technology (quasi-static CMOS logic).	ISCAS	2003	DBLP DOI BibTeX RDF
2	Yonghui Tang, Randall L. Geiger	A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti	A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.	ISLPED	2000	DBLP DOI BibTeX RDF	SDH, clock recovery, low power, optical communications
1	Hakjeon Bang, Jong-Oh Choi, Seong-Ro Lee, Chang-Soo Park	Adaptive Clock Recovery Mechanism Having Dynamic Frequency Drift and Buffer Level Control in Packet Switched Networks.	IEEE Communications Letters	2011	DBLP DOI BibTeX RDF
1	Ali Montazeri, Allen Webb, Kamran Kiasaleh	Low-Power Spectral-Line Clock Recovery Algorithm for SDR Applications.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Soojin Kim, Kyeongsoon Cho	Design of high-speed clock recovery circuit for burst-mode applications.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Chih-Hsing Lin, Jen-Ming Wu, Ching-Te Chiu, Shuo-Hung Hsu	A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Chi Fat Chan, Kong-Pang Pun, Ka Nang Leung, Jianping Guo, Lincoln Lai Kan Leung, Oliver Chiu-sing Choy	A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	István Haller, Zoltan Francisc Baruch	High-speed clock recovery for low-cost FPGAs.	DATE	2010	DBLP BibTeX RDF
1	Hossam Ali, Emad Hegazi	A low-jitter video clock recovery circuit.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Aymen Ghenim, Mohamed Ghorbel, Ahmed Ben Hamida	A full digital low power dpsk demodulator and clock recovery circuit for high data rate neural implants.	ICECS	2010	DBLP DOI BibTeX RDF
1	Shuai Lv, Yueming Lu, Yuefeng Ji	Short-delay clock recovery for CBR services in PTN.	IEEE Communications Letters	2009	DBLP DOI BibTeX RDF
1	Monika Jain, P. C. Jain, Sharad Jain, Ankit Jain	Novel Clock Recovery Module for MPEG-2 Transport Stream in Terrestrial Television.	JDCTA	2009	DBLP BibTeX RDF
1	Naim Ben-Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt	Clock recovery for a 40 Gb/s QPSK optical receiver.	ICECS	2009	DBLP DOI BibTeX RDF
1	Anthony Rowe, Vikram Gupta, Ragunathan Rajkumar	Low-power clock synchronization using electromagnetic energy radiating from AC power lines.	SenSys	2009	DBLP DOI BibTeX RDF	hardware clock synchronization, wireless sensor networks, sensor networks, synchronization
1	B. S. Sreeja, S. Radha	Design and implementation of MEMS based differential voltage controlled oscillator.	EIT	2009	DBLP DOI BibTeX RDF
1	Ching-Yuan Yang, Ken-Hao Chang	Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Takefumi Yoshikawa, Tetsuhiro Ogino, Makoto Nagata	Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	James Aweya, Delfin Y. Montuno, Michel Ouellette, Kent Felske	Analysis of a clock-recovery technique for circuit emulation services over packet networks.	Int. J. Communication Systems	2008	DBLP DOI BibTeX RDF
1	Zuojian Song, Haifeng Zhou, Ziwei Gen, Yoshitaka Takasaki	Dependence of Jitter Accumulation on Line Codes for Clock Recovery with Minimal Filtering.	AICT	2008	DBLP DOI BibTeX RDF
1	Merritt Miller, Greg Hoover, Forrest Brewer	Pulse-mode link for robust, high speed communications.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Zhongjun Wang, Yan Xin 0001, Masayuki Tomisawa	Phase Error Suppression for Multi-Band OFDM-Based UWB Systems.	VTC Spring	2008	DBLP DOI BibTeX RDF
1	Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici	Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit	CoRR	2007	DBLP BibTeX RDF
1	James Aweya, Delfin Y. Montuno, Michel Ouellette, Kent Felske	Clock recovery based on packet inter-arrival time averaging.	Computer Communications	2006	DBLP DOI BibTeX RDF
1	Youichi Fukada, Takeshi Yasuda, Shuji Komatsu, Koichi Saito, Yoichi Maeda, Yasuyuki Okumura	Adaptive Clock Recovery Method Utilizing Proportional-Integral-Derivative (PID) Control for Circuit Emulation.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Amr Elshazly, Khaled M. Sharaf	2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Pietro Savazzi, Paolo Gamba, Sergio Callegari	An All-Digital Clock Recovery Architecture for the BRAN Hiperaccess Uplink Receiver.	VTC Spring	2006	DBLP DOI BibTeX RDF
1	Nele Noels, Heidi Steendam, Marc Moeneclaey	Carrier and Clock Recovery in (Turbo-)Coded Systems: Cramér-Rao Bound and Synchronizer Performance.	EURASIP J. Adv. Sig. Proc.	2005	DBLP DOI BibTeX RDF
1	Hyung-Wook Jang, Sung-Sop Lee, Jin-Ku Kang	A clock recovery circuit using half-rate 4×-oversampling PD.	ISCAS	2005	DBLP DOI BibTeX RDF
1	A. Hughes, I. J. Fair	An Integrated Error Control and Constrained Sequence Code Based on Multimode Coding.	CNSR	2005	DBLP DOI BibTeX RDF
1	Ping-Ying Wang, Hsiang Ji Hsieh, Yung-Yu Lin, Meng-Ta Yang, Hsueh-Wu Kao	A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives.	ISCAS	2005	DBLP DOI BibTeX RDF
1	P. Gui, Fouad E. Kiamilev, X. Q. Wang, M. J. MacFadden, X. L. Wang, N. Waite, M. W. Haney, C. Kuznia	A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng	BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics.	ITC	2004	DBLP DOI BibTeX RDF
1	Francesco Centurelli, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti	A high-speed low-voltage phase detector for clock recovery from NRZ data.	ISCAS	2004	DBLP BibTeX RDF
1	Vijay Pillai, Harley Heinrich, K. V. S. Rao, Rene Martinez	A stacked antenna broad-band RFID front-end for UHF and microwave bands.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	dual front-end, schottky, RFID, stacked, passive, cascade, UHF, microwave
1	James Aweya, Michel Ouellette, Delfin Y. Montuno, Kent Felske	Circuit emulation services over ethernet-part 1: clock synchronization using timestamps.	Int. Journal of Network Management	2004	DBLP DOI BibTeX RDF
1	Scott Fairbanks, Simon W. Moore	Analog Micropipeline Rings for High Precision Timing.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Mike Li	Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs?	ITC	2004	DBLP DOI BibTeX RDF
1	Jianhua Liu, Jian Li	Parameter Estimation and Error Reduction for OFDM-Based WLANs.	IEEE Trans. Mob. Comput.	2004	DBLP DOI BibTeX RDF
1	Erdal Panayirci	Analysis of self-noise in a clock recovery system with a high-order nonlinearity.	IEEE Transactions on Information Theory	2003	DBLP DOI BibTeX RDF
1	Martin John Burbidge, Frederic Poullet, Jim Tijou, Andrew Richardson	Investigations for Minimum Invasion Digital Only Built-In "Ramp" Based Test Techniques for Charge Pump PLL's.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	test, DfT, BIST, jitter, phase locked loop
1	Seyed Reza Abdollahi, Sayfe Kiaei, Bertan Bakkaloglu, Seid Mehdi Fakhraie, R. Anvari, S. E. Abdollahi	An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Magnus Eckersand, Fredrik Franzon, Ken Filliter	Using At-Speed BIST to Test LVDS Serializer/Deserializer Function.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	LVDS, BIST, differential, At-speed
1	Weilian Su, Ian F. Akyildiz	The jitter time-stamp approach for clock recovery of real-time variable bit-rate traffic.	IEEE/ACM Trans. Netw.	2001	DBLP DOI BibTeX RDF	ATM adaptation layer 2 (AAL2), constant bit-rate (CBR), timing recovery, synchronization, ATM networks, variable bit-rate (VBR)
1	Antonio A. D'Amico, Nunzio Aldo D'Andrea, R. Regiannini	Efficient non-data-aided carrier and clock recovery for satellite DVB at very low signal-to-noise ratios.	IEEE Journal on Selected Areas in Communications	2001	DBLP DOI BibTeX RDF
1	Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu	A serial link transceiver for USB2 high-speed mode.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Alper Demir, Peter Feldmann	Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits.	DATE	2000	DBLP DOI BibTeX RDF
1	Christos Tryfonas, Anujan Varma	Timestamping Schemes for MPEG-2 Systems Layer and Their Effect on Receiver Clock Recovery.	IEEE Transactions on Multimedia	1999	DBLP DOI BibTeX RDF
1	Erdal Panayirci	Analysis of self noise in a clock recovery systems with a high order nonlinearity.	NSIP	1999	DBLP BibTeX RDF
1	Lizhong Sun, Tad A. Kwasniewski, Kris Iniewski	A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Tae Hun Kim, Beomsup Kim	Dual-loop Digital PLL Design for Adaptive Clock Recovery.	ASP-DAC	1998	DBLP BibTeX RDF
1	Yoshio Karasawa, Tomonori Kuroda, Hisato Iwai	Cycle slip in clock recovery on frequency-selective fading channels.	IEEE Transactions on Communications	1997	DBLP DOI BibTeX RDF
1	Xiaowen Wu, Shiqi Wu, Hairong Sun, Lemin Li	Clock Recovery for CBR Traffic in Wireless ATM Networks.	ICC	1997	DBLP BibTeX RDF
1	Zhigong Wang, Ulrich Langmann, Berthold G. Bosch	Multi-Gb/s Silicon Bipolar Clock Recovery IC.	IEEE Journal on Selected Areas in Communications	1991	DBLP DOI BibTeX RDF
1	Umberto Mengali, Nunzio Aldo D'Andrea, M. Moro	Pulse Shaping in Clock Recovery.	ICC	1986	DBLP BibTeX RDF