Search results for "clock tree"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Mely Chen Chi, Shih-Hsu Huang	A Reliable Clock Tree Design Methodology for ASIC Designs.	ISQED	2000	DBLP DOI BibTeX RDF	Clock tree design, Clock tree synthesis
3	Ying-Yu Chen, Chen Dong, Deming Chen	Clock tree synthesis under aggressive buffer insertion.	DAC	2010	DBLP DOI BibTeX RDF	slew, buffer insertion, buffer sizing, clock tree, maze routing
3	Tak-Yung Kim, Taewhan Kim	Clock tree synthesis with pre-bond testability for 3D stacked IC designs.	DAC	2010	DBLP DOI BibTeX RDF	optimization, routing, buffer insertion, 3D ICs, clock tree
3	Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang	Skew-aware polarity assignment in clock tree.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	peak current, polarity assignment, power/ground noise, Clock skew, clock tree
3	Rupesh S. Shelar	An efficent clustering algorithm for low power clock tree synthesis.	ISPD	2007	DBLP DOI BibTeX RDF	clustering, low power, clock tree synthesis
3	Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee	Zero-Skew Driven for RLC Clock Tree Construction in SoC.	ICITA	2005	DBLP DOI BibTeX RDF	RLC delay model, Upward propagation, SoC, Clock tree, Zero skew
3	Monica Donno, Enrico Macii, Luca Mazzoni	Power-aware clock tree planning.	ISPD	2004	DBLP DOI BibTeX RDF	clock tree synthesis and routing, physical design and optimization, low-power design, digital design
3	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.	ISPD	2003	DBLP DOI BibTeX RDF	?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew
3	Bing Lu, Jiang Hu, Gary Ellis, Haihua Su	Process variation aware clock tree routing.	ISPD	2003	DBLP DOI BibTeX RDF	VLSI, interconnect, physical design, clock tree synthesis
3	Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii	Clock-tree power optimization based on RTL clock-gating.	DAC	2003	DBLP DOI BibTeX RDF	clock-tree synthsis, low-power design
3	Chung-Wen Albert Tsao, Cheng-Kok Koh	UST/DME: a clock tree router for general skew constraints.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Useful Skew, feasible skew range, incremental skew scheduling, merging and embedding, merging region, clock tree
3	Chunhong Chen, Changjun Kang, Majid Sarrafzadeh	Activity-sensitive clock tree construction for low power.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, clock gating, clock tree, activity pattern
3	Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi	A practical clock tree synthesis for semi-synchronous circuits.	ISPD	2000	DBLP DOI BibTeX RDF	clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling
3	Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani	Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule
3	Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh	Activity-driven clock design for low power circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	Gated Clock Tree, Sleep Mode, Power minimization, Clock Tree
2	Xin-Wei Shih, Yao-Wen Chang	Fast timing-model independent buffered clock-tree synthesis.	DAC	2010	DBLP DOI BibTeX RDF
2	Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
2	Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Power efficient tree-based crosslinks for skew reduction.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crosslink, non-tree clock distribution network, power, mesh, skew, clock tree
2	Anand Rajaram, Raguram Damodaran, Arjun Rajagopal	Practical Clock Tree Robustness Signoff Metrics.	ISQED	2008	DBLP DOI BibTeX RDF
2	Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
2	Anand Rajaram, David Z. Pan	Robust chip-level clock tree synthesis for SOC designs.	DAC	2008	DBLP DOI BibTeX RDF	chip-level CTS, physical design, clock network
2	Jacob R. Minz, Xin Zhao, Sung Kyu Lim	Buffered clock tree synthesis for 3D ICs under thermal variations.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown	Clock tree synthesis with data-path sensitivity matching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Chunchen Liu, Junjie Su, Yiyu Shi	Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations.	ICCD	2008	DBLP DOI BibTeX RDF
2	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
2	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
2	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Vineet Wason, Rajeev Murgai, William W. Walker	An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal, Alexander Pratsch, Eike Schmidt	System level clock tree synthesis for power optimization.	DATE	2007	DBLP DOI BibTeX RDF
2	Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai	Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang	Skew aware polarity assignment in clock tree.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail	A self-adjusting clock tree architecture to cope with temperature variations.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Seongmoon Wang, Wenlong Wei	A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture.	ASP-DAC	2007	DBLP DOI BibTeX RDF	peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs
2	Arjun Rajagopal	Clock tree design challenges for robust and low power design.	ISPD	2006	DBLP DOI BibTeX RDF	NBTI, IR drop
2	Uday Padmanabhan, Janet Meiling Wang, Jiang Hu	Statistical clock tree routing for robustness to process variations.	ISPD	2006	DBLP DOI BibTeX RDF	routing, robustness, process variations, clock tree
2	Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee	Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino	Thermal resilient bounded-skew clock tree optimization methodology.	DATE	2006	DBLP DOI BibTeX RDF
2	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic thermal clock skew compensation using tunable delay buffers.	ISLPED	2006	DBLP DOI BibTeX RDF	temperature aware design methodology, tunable delay buffers, clock skew, clock tree
2	Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu	Minimizing peak current via opposite-phase clock tree.	DAC	2005	DBLP DOI BibTeX RDF	low power, physical design, clock network synthesis
2	Jeng-Liang Tsai, Charlie Chung-Ping Chen	Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Wai-Ching Douglas Lam, Cheng-Kok Koh	Process variation robust clock tree routing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Min Pan, Chris C. N. Chu, J. Morris Chang	Transition time bounded low-power clock tree construction.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh	Floorplanning with clock tree estimation.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Rishi Chaturvedi, Jiang Hu	Buffered Clock Tree for High Quality IC Design.	ISQED	2004	DBLP DOI BibTeX RDF
2	Dongsheng Wang, Peter Suaris, Nan-Chi Chou	A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy	Energy recovery clocking scheme and flip-flops for ultra low-energy applications.	ISLPED	2003	DBLP DOI BibTeX RDF	flip-flop, clock, clock tree, energy recovery, adiabatic
2	Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen	Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.	DAC	2002	DBLP DOI BibTeX RDF	di/dt noise, low-noise digital design, supply current shaping, optimization, substrate noise, clock distribution networks
2	Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling	Wavelet method for high-speed clock tree simulation.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou	A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Haksu Kim, Dian Zhou	An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto	Clock skew reduction in ASIC logic design: a methodology for clock tree management.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Zhaoyun Xing, Prithviraj Banerjee	A parallel algorithm for zero skew clock tree routing.	ISPD	1998	DBLP DOI BibTeX RDF
2	Ashok Vittal, Malgorzata Marek-Sadowska	Low-power buffered clock tree design.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
2	José Luis Neves, Eby G. Friedman	Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.	VLSI Signal Processing	1997	DBLP DOI BibTeX RDF
2	Andrew B. Kahng, Chung-Wen Albert Tsao	Planar-DME: a single-layer zero-skew clock tree router.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
2	Joe G. Xi, Wayne Wei-Ming Dai	Jitter-tolerant clock routing in two-phase synchronous systems.	ICCAD	1996	DBLP DOI BibTeX RDF	Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
2	Jae Chung, Chung-Kuan Cheng	Skew sensitivity minimization of buffered clock tree.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Dongjin Lee, Igor L. Markov	Obstacle-Aware Clock-Tree Shaping During Placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee	Discharge-path-based antenna effect detection and fixing for X-architecture clock tree.	Integration	2012	DBLP DOI BibTeX RDF
1	Yeh-Chi Chang, Chun-Kai Wang, Hung-Ming Chen	On construction low power and robust clock tree via slew budgeting.	ISPD	2012	DBLP DOI BibTeX RDF
1	Xin Zhao, Sung Kyu Lim	Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Pinaki Chakrabarti	Clock Tree Skew Minimization with Structured Routing.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee	Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi	Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Tak-Yung Kim, Taewhan Kim	Clock Tree synthesis for TSV-based 3D IC designs.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim	Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Anand Rajaram, David Z. Pan	Robust Chip-Level Clock Tree Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Hochang Jang, Deokjin Joo, Taewhan Kim	Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee	Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration.	Integration	2011	DBLP DOI BibTeX RDF
1	Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho	Pulsed-latch-based clock tree migration for dynamic power reduction.	ISLPED	2011	DBLP BibTeX RDF
1	Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin-Ngai Sze	Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Dongjin Lee, Igor L. Markov	Obstacle-aware clock-tree shaping during placement.	ISPD	2011	DBLP DOI BibTeX RDF
1	Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan	Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Xuchu Hu, Matthew R. Guthaus	Clock tree optimization for Electromagnetic Compatibility (EMC).	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Matthew R. Guthaus	Distributed LC resonant clock tree synthesis.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail	SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Siong Kiong Teng, Norhayati Soin	Low power clock gates optimization for clock tree distribution.	ISQED	2010	DBLP DOI BibTeX RDF
1	Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi	Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.	ISQED	2010	DBLP DOI BibTeX RDF
1	Ali M. Farhangi, Asim J. Al-Khalili, Dhamin Al-Khalili	Pattern-Driven Clock Tree Routing with Via Minimization.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Clock Tree Synthesis with XOR Gates for Polarity Assignment.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Krit Athikulwongse, Xin Zhao, Sung Kyu Lim	Buffered clock tree sizing for skew minimization under power and thermal budgets.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan	Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Tak-Yung Kim, Taewhan Kim	Clock tree embedding for 3D ICs.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen	Minimizing clock latency range in robust clock tree synthesis.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang	Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, David Z. Pan	PASAP: power aware structured ASIC placement.	ISLPED	2010	DBLP DOI BibTeX RDF	structured ASICS, low power, placement, regular fabrics
1	Ashutosh Chakraborty, David Z. Pan	Skew management of NBTI impacted gated clock trees.	ISPD	2010	DBLP DOI BibTeX RDF	clock skew, clock gating, NBTI
1	Davide Pandini, Guido A. Repetto, Vincenzo Sinisi	Clock-tree synthesis for low-EMI design.	J. Embedded Computing	2009	DBLP DOI BibTeX RDF
1	Monica Figueiredo, Rui L. Aguiar	Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim	Pre-bond testable low-power clock tree design for 3D stacked ICs.	ICCAD	2009	DBLP BibTeX RDF
1	Pei-Hsin Ho	Industrial clock design.	ISPD	2009	DBLP DOI BibTeX RDF	low power, variability, physical design, clock tree synthesis
1	Hochang Jang, Taewhan Kim	Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.	DAC	2009	DBLP DOI BibTeX RDF	clock synthesis, power/ground noise, buffer insertion
1	Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura	Lagrangian relaxation based register placement for high-performance circuits.	ISQED	2009	DBLP DOI BibTeX RDF
1	Wenting Hou, Dick Liu, Pei-Hsin Ho	Automatic register banking for low-power clock trees.	ISQED	2009	DBLP DOI BibTeX RDF
1	Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, Vipul Kadodwala	Early clock prototyping for design analysis and quality entitlement.	ISQED	2009	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Low Power Gated Clock Tree Driven Placement.	IEICE Transactions	2008	DBLP DOI BibTeX RDF