Search results for "code scheduling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Dingchao Li, Yuji Iwahori, Tatsuya Hayashi, Naohiro Ishii	A Spill Code Placement Framework for Code Scheduling.	LCPC	1998	DBLP DOI BibTeX RDF	Fine grain parallel architectures, program behavior analysis, compiler optimization, register spilling, code scheduling
2	Zhenmin Li, Taewhan Kim	Address Code Optimization Exploiting Code Scheduling in DSP Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir	Power-aware code scheduling for clusters of active disks.	ISLPED	2005	DBLP DOI BibTeX RDF	cluster of active disks (CAD), scheduling, compiler
2	Yoonseo Choi, Taewhan Kim	Address code optimization using code scheduling for digital signal processors.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker	Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.	MICRO	1996	DBLP BibTeX RDF	linear code regions, long-instruction-word machines, optimum scheduling, profile-driven instruction level parallel scheduling, profile-sensitive scheduler, ranking branch instructions, compiler optimization, scheduling heuristic, abstract model, optimising compilers, code scheduling
2	Tai M. Chung, Henry G. Dietz	Static scheduling of hard real-time code with instruction-level timing accuracy.	RTCSA	1996	DBLP DOI BibTeX RDF	timing fault, instruction-level timing accuracy, high-level language code, instruction-level, compiler code scheduling, genetic search algorithm, real-time systems, timing analysis, processor scheduling, search space
2	James R. Goodman, Wei-Chung Hsu	Code scheduling and register allocation in large basic blocks.	ICS	1988	DBLP DOI BibTeX RDF
1	Jaehyun Park, Jangmyung Lee	A Beacon Color Code Scheduling for the Localization of Multiple Robots.	IEEE Trans. Industrial Informatics	2011	DBLP DOI BibTeX RDF
1	Taylan Yemliha, Mahmut T. Kandemir, Ozcan Ozturk, Emre Kultursay, Sai Prashanth Muralidhara	Code Scheduling for Optimizing Parallelism and Data Locality.	Euro-Par	2010	DBLP DOI BibTeX RDF
1	Haitao Wei, Junqing Yu, Huafei Yu, Guang R. Gao	Minimizing communication in rate-optimal software pipelining for stream programs.	CGO	2010	DBLP DOI BibTeX RDF	dfbrook, multi-core, software pipelining, cell processor, stream programs
1	Víctor J. Jiménez, Lluís Vilanova, Isaac Gelado, Marisa Gil, Grigori Fursin, Nacho Navarro	Predictive Runtime Code Scheduling for Heterogeneous Architectures.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Eryk Laskowski, Marek Tudruj, Richard Olejnik, Bernard Toursel	Byte-code scheduling of Java programs with branches for desktop grid.	Future Generation Comp. Syst.	2007	DBLP DOI BibTeX RDF
1	Taewhan Kim, Jungeun Kim	Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Sebastian Winkel	Optimal versus Heuristic Global Code Scheduling.	MICRO	2007	DBLP DOI BibTeX RDF
1	Santosh G. Nagarakatte, R. Govindarajan	Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation.	CC	2007	DBLP DOI BibTeX RDF
1	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	An Overview of a Compiler for Mapping Software Binaries to Hardware.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Injong Rhee, Ajit Warrier, Jeongki Min, Lisong Xu	DRAND: : distributed randomized TDMA scheduling for wireless ad-hoc networks.	MobiHoc	2006	DBLP DOI BibTeX RDF	wireless sensor networks, medium access control, network performance
1	Jungeun Kim, Taewhan Kim	Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design.	DAC	2005	DBLP DOI BibTeX RDF	scheduling, binding, memory access
1	Eryk Laskowski, Marek Tudruj, Richard Olejnik, Bernard Toursel	Java Byte Code Scheduling Based on the Most-Often-Used-Paths in Programs with Branches.	ISPDC	2005	DBLP DOI BibTeX RDF
1	Xiaoru Dai, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew	A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion.	CGO	2005	DBLP DOI BibTeX RDF
1	Yoonseo Choi, Taewhan Kim	Address assignment in DSP code generation - an integrated approach.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Yoonseo Choi, Taewhan Kim	Address assignment combined with scheduling in DSP code generation.	DAC	2002	DBLP DOI BibTeX RDF	offset assignment, scheduling, code generation
1	Xiushan Feng, Alan J. Hu	Automatic formal verification for scheduled VLIW code.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	theory of equality with uninterpreted functions, formal verification, DSP, VLIW, symbolic execution
1	Cristiana Bolchini, Fabio Salice	A Software Methodology for Detecting Hardware Faults in VLIW Data Paths. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	Software code scheduling, VLIW processors, Hardware fault detection
1	Johan Runeson, Sven-Olof Nyström, Jan Sjödin	Optimizing Code Size through Procedural Abstraction.	LCTES	2000	DBLP DOI BibTeX RDF
1	Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey	Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF
1	John L. Ross, Shmuel Sagiv	Building a Bridge between Pointer Aliases and Program Dependences.	ESOP	1998	DBLP DOI BibTeX RDF
1	Akira Koseki, Yoshiaki Fukazawa, Hideaki Komatsu	A Register Allocation Technique Using Register Existence Graph. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Program Dependence Graph, Code Scheduling
1	Soo-Mook Moon, Kemal Ebcioglu	Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar
1	Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. Tavares Fernandes	Datapath Design for a VLIW Video Signal Processor.	HPCA	1997	DBLP DOI BibTeX RDF	datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design
1	Kenji Sayano, Tomonori Shirakawa	Pleiades: A Prototype of Inter-Processor Network Generation System.	ISPAN	1997	DBLP DOI BibTeX RDF
1	Pohua P. Chang, Dong-yuan Chen, Yong-Fong Lee, Youfeng Wu, Utpal Banerjee	Bidirectional Scheduling: A New Global Code Scheduling Approach.	LCPC	1996	DBLP DOI BibTeX RDF
1	Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown	Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
1	Franco Gasperoni, Uwe Schwiegelshohn	List Scheduling in the Presence of Branches: A Theoretical Evaluation.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
1	Pohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu	The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF
1	Pai H. Chou, Gaetano Borriello	Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems.	DAC	1995	DBLP DOI BibTeX RDF
1	Pohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu	Three Architecutral Models for Compiler-Controlled Speculative Execution.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	static code scheduling, superpipelining, exception handling, speculative execution, superscalar, Conditional branches, superblock
1	Richard Gerber, Seongsoo Hong	Compiling Real-Time Programs With Timing Constraint Refinement and Structural Code Motion.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	gated single assignment, Real-time, programming languages, compiler optimization, timing analysis, code motion, static single assignment, trace scheduling, code scheduling
1	Chi-Keung Luk	Memory disambiguation for general-purpose applications.	CASCON	1995	DBLP DOI BibTeX RDF
1	André Bakkers, Johan Sunter, Evert Ploeg	Automatic Generation of Scheduling and Communication Code in Real-Time Parallel Programs.	Workshop on Languages, Compilers, & Tools for Real-Time Systems	1995	DBLP DOI BibTeX RDF
1	Steven M. Kurlander, Todd A. Proebsting, Charles N. Fischer	Efficient Instruction Scheduling for Delayed-Load Architectures.	ACM Trans. Program. Lang. Syst.	1995	DBLP DOI BibTeX RDF
1	Gary S. Tyson, Matthew K. Farrens	Code scheduling for multiple instruction stream architectures.	International Journal of Parallel Programming	1994	DBLP DOI BibTeX RDF
1	David M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu	Dynamic Memory Disambiguation Using the Memory Conflict Buffer.	ASPLOS	1994	DBLP DOI BibTeX RDF
1	Steven M. Kurlander, Charles N. Fischer	Zero-cost Range Splitting.	PLDI	1994	DBLP DOI BibTeX RDF
1	Richard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu	Superblock formation using static program analysis.	MICRO	1993	DBLP DOI BibTeX RDF	optimization, VLIW, superscalar, static program analysis, superblock, code scheduling
1	Tokuzo Kiyohara, John C. Gyllenhaal	Code scheduling for VLIW/superscalar processors with limited register files.	MICRO	1992	DBLP DOI BibTeX RDF
1	Y. A. Frantsuzov	Code SCheduling Via Time Model.	IFIP Congress	1992	DBLP BibTeX RDF
1	Todd A. Proebsting, Charles N. Fischer	Linear-Time, Optimal Code Scheduling for Delayed-Load Architectures.	PLDI	1991	DBLP DOI BibTeX RDF
1	Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu	Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.	MICRO	1991	DBLP DOI BibTeX RDF
1	Ashar Nisar, Henry G. Dietz	Optimal Code Scheduling for Multiple-Pipeline Processors.	ICPP	1990	DBLP BibTeX RDF
1	Guang R. Gao, Herbert H. J. Hum, Yue-Bong Wong	An Efficient Scheme for Fine-Grain Software Pipelining.	CONPAR	1990	DBLP DOI BibTeX RDF
1	Hubert C. Delany	Ray tracing on a connection machine.	ICS	1988	DBLP DOI BibTeX RDF	CM-1, CRAY-1
1	Pohua P. Chang, Wen-mei W. Hwu	Trace selection for compiling large C application programs to microcode.	MICRO	1988	DBLP DOI BibTeX RDF	C
1	Christine Eisenbeis, William Jalby, Alain Lichnewsky	Squeezing more CPU performance out of a Cray-2 by Vector block scheduling.	SC	1988	DBLP BibTeX RDF