Search results for "coherent caches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparing memory systems for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches
2	Theodore Johnson	A performance comparison of fast distributed mutual exclusion algorithms. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	O(log n) messages, distributed virtual memory, computational complexity, distributed algorithms, distributed algorithms, software performance evaluation, performance comparison, distributed object systems, distributed synchronization, mutual exclusion algorithms, coherent caches
2	Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, John L. Hennessy	The DASH Prototype: Logic Overhead and Performance.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	DASH project, large-scale shared-memory multiprocessors, directory-based cachecoherence, reference behavior, DASHprotocol, atomic tests, performance evaluation, parallel programming, shared memory systems, storage management, buffer storage, hardware performance monitor, coherent caches
1	David Tarjan, Kevin Skadron	The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches.	SC	2010	DBLP DOI BibTeX RDF
1	Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry Ponomarev	MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches.	SIGARCH Computer Architecture News	2009	DBLP DOI BibTeX RDF
1	Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev	MPTLsim: a simulator for X86 multicore processors.	DAC	2009	DBLP DOI BibTeX RDF	simulator, microprocessor, coherent cache
1	Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan	CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA accelerators, c-to-gates, FPGA, high-performance computing, reconfigurable computing
1	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparative evaluation of memory models for chip multiprocessors.	TACO	2008	DBLP DOI BibTeX RDF	streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations
1	Sundeep Narravula, Pavan Balaji, Karthikeyan Vaidyanathan, Hyun-Wook Jin, Dhabaleswar K. Panda	Architecture for caching responses with multiple dynamic dependencies in multi-tier data-centers over InfiniBand.	CCGRID	2005	DBLP DOI BibTeX RDF
1	Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee	Reducing False Sharing and Improving Spatial Locality in a Unified Compilation Framework.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	loop and memory layout transformations, shared-memory multiprocessors, Data reuse, cache locality, false sharing
1	T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi	Speculative Versioning Cache.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	Speculative memory, snooping cache coherence protocols, speculative versioning, memory disambiguation
1	Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee	On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	loop and memory layout transformations, shared-memory multiprocessors, data reuse, cache locality, false sharing
1	Tao Li, Ben-Wei Rong	A Versatile Directory Scheme(Dir2NB+L) and Its Implementation on BY91-1 Multiprocessors System.	APDC	1997	DBLP DOI BibTeX RDF
1	J. Morris, R. R. Gregg, D. Herbert, J. McCoull	Reducing Overheads in Distributed Shared Memory Systems.	HICSS	1997	DBLP DOI BibTeX RDF
1	Lawrence Williams	Simulating the DASH Architecture in HASE.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF
1	Chun Xia, Josep Torrellas	Improving the Data Cache Performance of Multiprocessor Operating Systems.	HPCA	1996	DBLP DOI BibTeX RDF	data cache performance, operating system effect on caches, bus-based multiprocessor, address trace evaluation, block operations, latency hiding
1	Jaswinder Pal Singh, John L. Hennessy, Anoop Gupta	Implications of Hierarchical N-Body Methods for Multiprocessor Architectures	ACM Trans. Comput. Syst.	1995	DBLP DOI BibTeX RDF	N-body methods, locality, message passing, shared memory, scaling, parallel applications, parallel computer architecture, shared address space, communication abstractions
1	Yong-Kim Chong, Kai Hwang	Performance Analysis of Four Memory Consistency Models for Multithreaded Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	latency hiding techniques, performance evaluation, Distributed shared memory, stochastic Petri nets, multithreaded processors, memory consistency models, context switching, scalable multiprocessors
1	Cheng Che Chen, Jaswinder Pal Singh, William B. Poland, Russ B. Altman	Parallel protein structure determination from uncertain data.	SC	1994	DBLP BibTeX RDF
1	Timothy Mann, Andrew Birrell, Andy Hisgen, Charles Jerian, Garret Swart	A Coherent Distributed File Cache with Directory Write-Behind.	ACM Trans. Comput. Syst.	1994	DBLP DOI BibTeX RDF	write-behind, coherence, file caching
1	David M. Koppelman	Reducing PE/Memory Traffic in Multiprocessors by the Difference Coding of Memory Addresses.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	memory traffic, difference coding, memory addresses, shared memory parallel computer, trace-drivensimulation, traffic volume, lower cost, lower latency network, networklatency, virtual machines, multiprocessors, message passing, multiprocessor interconnection networks, memories, shared memory systems, storage management, buffer storage, processing elements, coherent cache
1	Cezary Dubnicki, Thomas J. LeBlanc	Adjustable Block Size Coherent Caches.	ISCA	1992	DBLP DOI BibTeX RDF