Search results for "combinational circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi	Formal Verification Of Self-Testing Properties Of Combinational Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	self-testing properties, logic function manipulation, decision function, output code words, self-checking logic, mutiple-input multiple-output circuit, fault tolerance, formal verification, combinational circuits, combinational circuits, binary decision diagrams, stuck-at faults, satisfiability problem, characteristic functions, Berger code
4	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
4	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu	Generation of tenacious tests for small gate delay faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
4	Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey	A simple technique for locating gate-level faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
4	Xunwei Wu, Xiexiong Chen, Jizhong Shen	Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	race-hazard, skip-hazard, multivalued combinational circuits, race hazards, AND/OR expression, skip hazard, multivalued circuits, fast transition, small load capacitor, combinational circuits, multivalued logic circuits, hazards and race conditions, input signals
4	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults
4	Sreejit Chakravarty, Yiming Gong	Voting model based diagnosis of bridging faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure
4	Abdel-Fattah Yousif, Jun Gu	Concurrent automatic test pattern generation algorithm for combinational circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	concurrent automatic test pattern generation algorithm, global computations techniques, concurrent search, ISCAS'85, ISCAS'89 benchmarks, computational complexity, logic testing, NP-hard, combinational circuits, combinational circuits, automatic testing
3	Aiman H. El-Maleh, Yahya E. Osais	Test vector decomposition-based static compaction algorithms for combinational circuits.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Static compaction, class-based clustering, independent fault clustering, test vector decomposition, taxonomy, combinational circuits
3	Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
3	Emil Gizdarski, Hideo Fujiwara	Spirit: satisfiability problem implementation for redundancy identification and test generation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
3	Irith Pomeranz, Sudhakar M. Reddy	Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	test generation, combinational circuits, stuck-at faults, logic simulation
3	Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham	Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.	VTS	1996	DBLP DOI BibTeX RDF	waveform analysis, nonrobust tests, stuck-fault detection, signal waveform analysis, signal waveform integration, directed random test generation techniques, fault diagnosis, logic testing, redundancy, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, detectability, fault coverage, test application time, redundant faults
3	Valery A. Vardanian	On completely robust path delay fault testable realization of logic functions.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions
3	Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu	Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron beam testing, multiple fault diagnosis, sensitized paths, EB testing, TP-1, TP-2, TP-3, TP-4, electron-beam tester, internal lines, VLSI, fault diagnosis, logic testing, combinational circuits, combinational circuits, fault location, fault location, stuck-at faults, diagnostic resolution
3	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
3	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
3	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
3	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
3	Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak	An improved output compaction technique for built-in self-test in VLSI circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
3	A. Pal, R. K. Gorai, V. V. S. S. Raju	Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach
3	Wuudiann Ke, Premachandran R. Menon	Multifault testability of delay-testable circuits.	VTS	1995	DBLP DOI BibTeX RDF	delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
3	Angela Krstic, Kwang-Ting Cheng	Generation of high quality tests for functional sensitizable paths.	VTS	1995	DBLP DOI BibTeX RDF	high quality tests, functional sensitizable paths, long paths, untestable paths, faulty conditions, test derivation, logic testing, delays, timing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, delay testing, test vectors, timing information
3	S. A. Ali, G. Robert Redinbo	Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	tight lower bounds, internal signal lines, fault diagnosis, logic testing, combinational circuits, combinational circuits, random testing, detection probabilities, single faults
2	Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha	Statistical noise margin estimation for sub-threshold combinational circuits.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Yu-Shiang Lin, Dennis Sylvester	Runtime leakage power estimation technique for combinational circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations
2	Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.	DATE	2007	DBLP DOI BibTeX RDF
2	Hans-Georg Breunig	The Complexity of Membership Problems for Circuits over Sets of Positive Numbers.	FCT	2007	DBLP DOI BibTeX RDF	Computational complexity, Combinational circuits, Arithmetic circuits
2	Audhild Vaaje	Theorems for Fault Collapsing in Combinational Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	Boolean function, combinational circuit, monotonic function, fault collapsing
2	Jialin Mi, Chunhong Chen	Power-Oriented Delay Budgeting for Combinational Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester	An efficient static algorithm for computing the soft error rates of combinational circuits.	DATE	2006	DBLP DOI BibTeX RDF
2	Jialin Mi, Chunhong Chen, H. K. Kwan	Power-oriented delay budgeting for combinational circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Á. Michels, Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro	SET Fault Tolerant Combinational Circuits Based on Majority Logic.	DFT	2006	DBLP DOI BibTeX RDF
2	Dimitrios Bountas, Georgios I. Stamoulis	CARROT - A Tool for Fast and Accurate Soft Error Rate Estimation.	SAMOS	2006	DBLP DOI BibTeX RDF	simulation, combinational circuits, SER
2	Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang	An efficient combinationality check technique for the synthesis of cyclic combinational circuits.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Walter Dosch	Designing Combinational Circuits with List Homomorphisms.	SERA	2005	DBLP DOI BibTeX RDF	functional hardware description, list homomorphism, iterative network, parity generator, priority resolution, High-level synthesis, comparator, tree network
2	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Soft Delay Error Effects in CMOS Combinational Circuits.	VTS	2004	DBLP DOI BibTeX RDF	Soft delay, single event upsets (SEUs), soft error rate (SER), soft errors
2	Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana	Fault equivalence identification in combinational circuits using implication and evaluation techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	João P. Marques Silva, Luís Guerra e Silva	Solving Satisfiability in Combinational Circuits.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
2	Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns	Leakage and leakage sensitivity computation for combinational circuits.	ISLPED	2003	DBLP DOI BibTeX RDF	iddq analysis, sensitivity, power estimation, leakage power
2	Ramzi Ben Salah, Marius Bozga, Oded Maler	On Timing Analysis of Combinational Circuits.	FORMATS	2003	DBLP DOI BibTeX RDF
2	Marc D. Riedel, Jehoshua Bruck	The synthesis of cyclic combinational circuits.	DAC	2003	DBLP DOI BibTeX RDF	feedback, logic synthesis, cycles, combinational logic
2	Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu	On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Chandramouli Gopalakrishnan, Srinivas Katkoori	Power Optimization of Combinational Circuits by Input Transformations.	DELTA	2002	DBLP DOI BibTeX RDF
2	Fatih Kocan, Daniel G. Saab	ATPG for combinational circuits on configurable hardware.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Ilker Hamzaoglu, Janak H. Patel	Test set compaction algorithms for combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
2	Byungwoo Choi, D. M. H. Walker	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.	VTS	2000	DBLP DOI BibTeX RDF	interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
2	Dirk W. Hoffmann, Thomas Kropf	Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits.	DATE	2000	DBLP DOI BibTeX RDF
2	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
2	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
2	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.	VTS	2000	DBLP DOI BibTeX RDF	Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
2	Irith Pomeranz, Sudhakar M. Reddy	A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	test generation, Combinational circuits, genetic optimization
2	Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen	Equivalence checking of combinational circuits using Boolean expression diagrams.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Vijay Sundararajan, Keshab K. Parhi	Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.	ARVLSI	1999	DBLP DOI BibTeX RDF	Gate-resizing, Buffer-redistribution, near-optimal, library-specific, optimal, low-power
2	Zhide Zeng, Jihua Chen, Hefeng Cao	Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	finite backtracking test pattern generation, n to 1 tightly coupled integration mode, parallel-pattern, single-fault propagation, ultra large scale combinational circuit (ULSCC
2	Luís Guerra e Silva, Luis Miguel Silveira, João P. Marques Silva	Algorithms for Solving Boolean Satisfiability in Combinational Circuits.	DATE	1999	DBLP DOI BibTeX RDF	Circuit Delay Computation, Test Pattern Generation, Boolean Satisfiability, Circuit Satisfiability
2	Irith Pomeranz, Sudhakar M. Reddy	Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	test generation, fault simulation, stuck-at faults, bridging faults, circuit partitioning
2	Yen-Chun Lin, Chao-Cheng Shih	A New Class of Depth-Size Optimal Parallel Prefix Circuits.	The Journal of Supercomputing	1999	DBLP DOI BibTeX RDF	depth-size optimal, unbounded fan-out, VLSI, Combinational circuits, parallel prefix
2	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests
2	Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy	Techniques for minimizing power dissipation in scan and combinational circuits during test application.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Design-for-testability for path delay faults in large combinational circuits using test points.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	V. V. Saposhnikov, A. A. Morosov, Vl. V. Saposhnikov, Michael Gössel	A New Design Method for Self-Checking Unidirectional Combinational Circuits.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF
2	Donatella Sciuto, Cristina Silvano, Renato Stefanelli	Systematic AUED Codes for Self-Checking Architectures. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	AUED Codes, Self-Checking Combinational Circuits, Stuck-at Faults, Unidirectional Errors
2	Aarti Gupta, Pranav Ashar	Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.	VLSI Design	1998	DBLP DOI BibTeX RDF	ATPG techniques, circuit similarity, formal verification, combinational circuits, Boolean satisfiability (SAT), combinational equivalence checking, Binary Decision Diagrams (BDDs)
2	Yong Je Lim, Mani Soma	Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Ayman M. Wahba, Dominique Borrione	Connection error location and correction in combinational circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
2	Hoon Choi, Seung Ho Hwang	Improving the accuracy of support-set finding method for power estimation of combinational circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
2	Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton	Approximate timing analysis of combinational circuits under the XBD0 model.	ICCAD	1997	DBLP DOI BibTeX RDF	delay computation, timing analysis, False path
2	Ramesh C. Tekumalla, Premachandran R. Menon	Test generation for primitive path delay faults in combinational circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	Sensitizing cubes, static sensitizability, primitive faults, test generation
2	Yiming Gong, Sreejit Chakravarty	Using fault sampling to compute I/sub DDQ/ diagnostic test set.	VTS	1997	DBLP DOI BibTeX RDF	fault sampling, IDDQ diagnostic test set generation, combinational circuits, combinational circuit, bridging faults
2	Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada	Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	supply current testing, D-frontier, test generation, IDDQ testing, PODEM
2	Vishwani D. Agrawal, David Lee	Characteristic polynomial method for verification and test of combinational circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	combinational circuit test, randomly selected integers, input variables, integer-valued transform functions, fixed domain, multiple samples, randomly selected real numbers, output logic, logic testing, probability, Boolean functions, Boolean functions, combinational circuits, polynomials, error probability, characteristic polynomial
2	Sunil R. Das, N. Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
2	Dimitrios Kagaris, Spyros Tragoudas	Generating deterministic unordered test patterns with counters.	VTS	1996	DBLP DOI BibTeX RDF	counting circuits, deterministic unordered test patterns, counter-based schemes, built-in mechanisms, test pattern generation session, ISCAS'85 benchmarks, logic testing, built-in self test, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, hardware overhead
2	Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz	On minimizing the number of test points needed to achieve complete robust path delay fault testability.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion
2	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Jau-Shien Chang, Chen-Shang Lin	Test set compaction for combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Alessandro Bogliolo, Maurizio Damiani	Synthesis of combinational circuits with special fault-handling capabilitie.	VTS	1995	DBLP DOI BibTeX RDF	combinational circuit synthesis, fault-handling capabilities, internal faults, multilevel logic optimization process, logic testing, redundancy, redundancy, design for testability, logic design, combinational circuits, logic CAD, multivalued logic, circuit optimisation, self-checking circuits, circuit reliability, fault-tolerant circuits
2	Irith Pomeranz, Sudhakar M. Reddy	Static compaction for two-pattern test sets.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults
2	Wen Ching Wu, Chung-Len Lee, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
2	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
2	B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh	A new methodology for the design of low-cost fail safe circuits and networks.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-cost fail safe circuits, safety critical electronic systems, input-output encoding problems, output encoding technique, low-cost design, systematic framework, graph theory, design methodology, encoding, combinational circuits, combinational circuits, graph embedding, graceful degradation, logic partitioning
2	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
2	Andrej Zemva, Franc Brglez	Detectable perturbations: a paradigm for technology-specific multi-fault test generation.	VTS	1995	DBLP DOI BibTeX RDF	detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
2	Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer	SWiTEST: a switch level test generation system for CMOS combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Sharad Malik	Analysis of cyclic combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Premachandran R. Menon, Hitesh Ahuja, Mohan Harihara	Redundancy identification and removal in combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton	A redesign technique for combinational circuits based on gate reconnections.	ICCAD	1994	DBLP DOI BibTeX RDF
2	Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen	A cell-based power estimation in CMOS combinational circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
2	Ohyoung Song, Premachandran R. Menon	Acceleration of trace-based fault simulation of combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
2	Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya	Logical redundancies in irredundant combinational circuits.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	irredundancy, testing, Boolean functions, combinational circuits, stuck-at faults, fanouts
2	Zaifu Zhang, Robert D. McLeod, Witold Pedrycz	A neural network algorithm for testing stuck-open faults in CMOS combinational circuits.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	stuck-open and gate delay faults, Neural networks, test pattern generation
2	El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny	On the generation of test patterns for multiple faults.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	Combinational circuits, stuck-at faults, test pattern generation, multiple faults, fault analysis
2	George Markowsky	Bounding fault detection probabilities in combinational circuits.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	Bounding probabilities, safety factor heuristic, testing, detection probability
2	Hyung Ki Lee, Dong Sam Ha	SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.	DAC	1990	DBLP DOI BibTeX RDF
2	Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz	The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	minimum test sets, monotone combinational circuits, minimum complete test set, monotone PLAs, computational complexity, complexity, logic testing, NP-complete, logic arrays, combinatorial circuits, literals
2	Bhargab B. Bhattacharya, Sharad C. Seth	Design of Parity Testable Combinational Circuits.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	parity testable combinational circuits, maximal supergates, single external test-mode pin, logic testing, integrated circuit testing, design for testability, integrated logic circuits, combinatorial circuits
2	Hyung Ki Lee, Dong Sam Ha, K. Kim	Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits.	DAC	1989	DBLP DOI BibTeX RDF
2	Yoshihiro Tohma, Kenji Goto	Test Generation for Large-Scale Combinational Circuits by Using Prolog.	LP	1987	DBLP DOI BibTeX RDF	Test, Prolog, Knowledge, Module, Acceleration
2	A. R. Virupakshia, V. C. V. Pratapa Reddy	A Simple Random Test Procedure for Detecion of Single Intermittent Fault in Combinational Circuits.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	intermittent fault detection, Combinational circuits, random testing