Search results for "compact modeling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu	Compact Modeling of Variation in FinFET SRAM Cells.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	multigate MOSFETs, variability, design for manufacturing, SRAM, design and test, FinFET, compact modeling
2	Binjie Cheng, Daryoosh Dideban, Negin Moezi, Campbell Millar, Gareth Roy, Xingsheng Wang, Scott Roy, Asen Asenov	Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	statistical variability, statistical compact modeling, design and test, MOSFET, mismatch
2	Arne von Drathen	Compact modeling of manufacturing systems with petri nets.	SMC	2007	DBLP DOI BibTeX RDF
2	Junjun Li, S. Joshi, R. Barnes, E. Rosenbaum	Compact modeling of on-chip ESD protection devices using Verilog-A.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Zhi-Qiang Lu, Feng-Chang Lai	Compact Modeling of MOSFETs Channel Noise for Low-Noise RF ICs Design.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar	Table look-up based compact modeling for on-chip interconnect timing and noise analysis.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Hai Wang, Sheldon X.-D. Tan, Ryan Rakib	Compact Modeling of Interconnect Circuits over Wide Frequency Band by Adaptive Complex-Valued Sampling Method.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
1	Patrick Le Maitre, Melanie Brocard, Alexis Farcy, Jean-Claude Marin	Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix.	ISQED	2012	DBLP DOI BibTeX RDF
1	Saeed Mohammadi, Ali Afzali-Kusha	Compact modeling of short-channel effects in symmetric and asymmetric 3-T/4-T double gate MOSFETs.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Wei Wang, Huaxin Lu, Jooyoung Song, Shih-Hsien Lo, Yuan Taur	Compact modeling of quantum effects in symmetric double-gate MOSFETs.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	Bradley N. Bond, Zohaib Mahmood, Yan Li, Ranko Sredojevic, Alexandre Megretski, Vladimir Stojanovic, Yehuda Avniel, Luca Daniel	Compact Modeling of Nonlinear Analog Circuits Using System Identification via Semidefinite Programming and Incremental Stability Certification.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Djamila Aouada, Hamid Krim	Squigraphs for Fine and Compact Modeling of 3-D Shapes.	IEEE Transactions on Image Processing	2010	DBLP DOI BibTeX RDF
1	Yongchan Ban, David Z. Pan	Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography.	DAC	2010	DBLP DOI BibTeX RDF	optimization, VLSI, DFM, variation, lithography, contact
1	Bradley N. Bond, Luca Daniel	Automated compact dynamical modeling: an enabling tool for analog designers.	DAC	2010	DBLP DOI BibTeX RDF	parameterized modeling, semidefinite programming, model reduction, analog design, compact modeling
1	Samar K. Saha	Modeling Process Variability in Scaled CMOS Technology.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	compact variability modeling, gate-oxide thickness variability, high-k dielectric, line-edge roughness, polysilicon granularity, random discrete dopants, scaled CMOS technology, statistical compact modeling, design and test, process variability, metal gate
1	Asha Balijepalli, Joseph Ervin, W. Lepkowski, Yu Cao, T. J. Thornton	Compact modeling of a PD SOI MESFET for wide temperature designs.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Jooyoung Song, Bo Yu, Yu Yuan, Yuan Taur	A Review on Compact Modeling of Multiple-Gate MOSFETs.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Yun Ye, Frank Liu, Min Chen, Yu Cao	Variability analysis under layout pattern-dependent rapid-thermal annealing process.	DAC	2009	DBLP DOI BibTeX RDF	dopant activation, layout pattern, rapid-thermal annealing, threshold voltage variation, physical design
1	E. Miranda	Compact modeling of the non-linear post-breakdown current in thin gate oxides using the generalized diode equation.	Microelectronics Reliability	2008	DBLP DOI BibTeX RDF
1	Cristina Castejón, Dolores Blanco, Luis Moreno	Compact Modeling Technique for Outdoor Navigation.	IEEE Transactions on Systems, Man, and Cybernetics, Part A	2008	DBLP DOI BibTeX RDF
1	Yogesh Singh Chauhan, Dimitrios Tsamados, Nicolas Abelé, C. Eggimann, Michel J. Declercq, Adrian M. Ionescu	Compact Modeling of Suspended Gate FET.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	ChenMing Hu	BSIM - making the first international standard MOSFET model.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	BSIM, MOS, compact modeling
1	Sheraz Khan, Benoit Cottereau, Richard M. Leahy, John C. Mosher, Habib Ammari, Sylvain Baillet	A two-step imaging procedure for MEG characterization of cortical currents: Location and spatial extent.	ISBI	2008	DBLP DOI BibTeX RDF
1	Esa Alhoniemi, Antti Honkela, Krista Lagus, Santeri Jeremias Seppä, Paul Wagner, Harri Valpola	Compact Modeling of Data Using Independent Variable Group Analysis.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	Asha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton	Compact Modeling of a PD SOI MESFET for Wide Temperature Designs.	ISQED	2007	DBLP DOI BibTeX RDF
1	Asha Balijepalli, Saurabh Sinha, Yu Cao	Compact modeling of carbon nanotube transistor for early stage process-design exploration.	ISLPED	2007	DBLP DOI BibTeX RDF	optimum delay, schottky-barrier, surface potential, modeling, process variability, CNT
1	Vladimir Zolotov, Jinjun Xiong, Soroush Abbaspour, David J. Hathaway, Chandu Visweswariah	Compact modeling of variational waveforms.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Azad Naeemi, James D. Meindl	Carbon nanotube interconnects.	ISPD	2007	DBLP DOI BibTeX RDF	quantum wires, crosstalk, inductance, repeaters, molecular electronics, system analysis and design, system optimization
1	Jeffrey Rambo, Yogendra Joshi	Modeling of data center airflow and heat transfer: State of the art and future trends.	Distributed and Parallel Databases	2007	DBLP DOI BibTeX RDF	Data center, Thermal modeling, Reduced order models
1	F. Pregaldiny, Christophe Lallement, B. Diagne, J.-M. Sallese, François Krummenacher	Compact Modeling of Emerging Technologies with VHDL-AMS.	FDL	2006	DBLP BibTeX RDF
1	Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet	Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies.	MoDELS	2005	DBLP DOI BibTeX RDF
1	Vishal P. Trivedi, Jerry G. Fossum, Leo Mathew, Murshed M. Chowdhury, Weimin Zhang, Glenn O. Workman, Bich-Yen Nguyen	Physics-based compact modeling for nonclassical CMOS.	ICCAD	2005	DBLP BibTeX RDF
1	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy	Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Jean-Paul Comet, Hanna Klaudel, Stéphane Liauzu	Modeling Multi-valued Genetic Regulatory Networks Using High-Level Petri Nets.	ICATPN	2005	DBLP DOI BibTeX RDF
1	Bhaskar Mukherjee, Lei Wang, Andrea Pacelli	A practical approach to modeling skin effect in on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	interconnects, circuit simulation, skin effect
1	Sopan Joshi, Elyse Rosenbaum	Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation.	Microelectronics Reliability	2003	DBLP DOI BibTeX RDF
1	Mansun Chan, Xuemei Xi, Jin He, Kanyu M. Cao, Mohan V. Dunga, Ali M. Niknejad, Ping K. Ko, Chenming Hu	Practical compact modeling approaches and options for sub-0.1 mum CMOS technologies.	Microelectronics Reliability	2003	DBLP DOI BibTeX RDF
1	Tom Dhaene	Self-Organizing Compact Modeling Methodology for High-Speed Passive Electrical Interconnection Structures.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.	DAC	2003	DBLP DOI BibTeX RDF	doping profiles, leakage, tunneling, threshold voltage
1	Garrett R. Yaun, Christopher D. Carothers, Shivkumar Kalyanaraman	Large-Scale TCP Models Using Optimistic Parallel Simulation.	PADS	2003	DBLP DOI BibTeX RDF
1	TingYen Chiang, Kaustav Banerjee, Krishna Saraswat	Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects.	ICCAD	2001	DBLP BibTeX RDF
1	Masanori Kuzuno, Toshihiko Nishio, Koji Koyamada	A thermal compact modeling method using Response Surface Methodology with Genetic Algorithm.	PDPTA	2000	DBLP BibTeX RDF
1	Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens	Compact Modeling of Nonlinear Distortion in Analog Communication Circuits.	DATE	2000	DBLP DOI BibTeX RDF
1	R. Lowther	Compact modeling of interconnect and substrate coupling at GHz frequencies.	ISCAS	1999	DBLP DOI BibTeX RDF
1	David T. Zweidinger, Sang-Gug Lee, Robert M. Fox	Compact modeling of BJT self-heating in SPICE.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Mohamed Bettaz, Mourad Maouche, M. Soulami, Madani Boukebeche	Compact Modeling and Rapid Prototyping of Communication Software with ECATNets: A Case Study.	MASCOTS	1993	DBLP BibTeX RDF