The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for phrase compensation paths (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1996 (1) 1997 (2) 1999 (1)
Publication types (Num. hits)
article(1) inproceedings(3)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 12 occurrences of 11 keywords

Results
Found 4 publication records. Showing 4 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
2Theodora A. Varvarigou, Miltiades E. Anagnostou, Sudhir R. Ahuja Reconfiguration Models and Algorithms for Stateful Interactive Processes. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Reconfiguration of stateful processes, compensation paths, optimal centralized algorithms, suboptimal distributed and hybrid algorithms, polynomial-time algorithms
2Itsuo Takanami, Tadayoshi Horita Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. (PDF / PS) Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays
1Itsuo Takanami, Tadayoshi Horita A built-in self-reconfigurable scheme for 3D mesh arrays. Search on Bibsonomy ISPAN The full citation details ... 1997 DBLP  DOI  BibTeX  RDF fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures
1Issei Numata, Susumu Horiguchi Efficient reconfiguration scheme for mesh-connected network: the recursive shift approach. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF mesh-connected network, recursive shift, faulty processing elements, mesh arrays, redundant processing elements, fault tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, reconfigurable architectures, massively parallel system, reconfiguration scheme
Displaying result #1 - #4 of 4 (100 per page; Change: )
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.