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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 12 occurrences of 11 keywords
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Results
Found 4 publication records. Showing 4 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Theodora A. Varvarigou, Miltiades E. Anagnostou, Sudhir R. Ahuja |
Reconfiguration Models and Algorithms for Stateful Interactive Processes.  |
IEEE Trans. Software Eng.  |
1999 |
DBLP DOI BibTeX RDF |
Reconfiguration of stateful processes, compensation paths, optimal centralized algorithms, suboptimal distributed and hybrid algorithms, polynomial-time algorithms |
| 2 | Itsuo Takanami, Tadayoshi Horita |
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. (PDF / PS)  |
DFT  |
1997 |
DBLP DOI BibTeX RDF |
self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays |
| 1 | Itsuo Takanami, Tadayoshi Horita |
A built-in self-reconfigurable scheme for 3D mesh arrays.  |
ISPAN  |
1997 |
DBLP DOI BibTeX RDF |
fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures |
| 1 | Issei Numata, Susumu Horiguchi |
Efficient reconfiguration scheme for mesh-connected network: the recursive shift approach.  |
ISPAN  |
1996 |
DBLP DOI BibTeX RDF |
mesh-connected network, recursive shift, faulty processing elements, mesh arrays, redundant processing elements, fault tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, reconfigurable architectures, massively parallel system, reconfiguration scheme |
Displaying result #1 - #4 of 4 (100 per page; Change: )
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