Search results for "compiler scheduling"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hyunchul Park, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-seok Kim	Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.	PACT	2008	DBLP DOI BibTeX RDF	operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture
1	Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan, Todd C. Mowry	Compiler and hardware support for reducing the synchronization of speculative threads.	TACO	2008	DBLP DOI BibTeX RDF	automatic parallelization, instruction scheduling, Thread-level speculation, chip-multiprocessing
1	Rahul Nagpal, Y. N. Srikant	Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW Architectures.	HiPC	2007	DBLP DOI BibTeX RDF
1	Katherine E. Coons, Xia Chen, Doug Burger, Kathryn S. McKinley, Sundeep K. Kushwaha	A spatial path scheduling algorithm for EDGE architectures.	ASPLOS	2006	DBLP DOI BibTeX RDF	EDGE architecture, path scheduling, simulated annealing, instruction scheduling
1	Hyunchul Park, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke	Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.	CASES	2006	DBLP DOI BibTeX RDF	graph embedding, modulo scheduling, coarse-grained reconfigurable architecture
1	Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Compiler-directed thermal management for VLIW functional units.	LCTES	2006	DBLP DOI BibTeX RDF	VLIW, thermal, IPC
1	Minyi Guo	Keynote Address: Energy-Aware Compiler Scheduling for VLIW Embedded Software.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
1	Mark Heffernan, Kent D. Wilken	Data-Dependency Graph Transformations for Instruction Scheduling.	J. Scheduling	2005	DBLP DOI BibTeX RDF	compiler scheduling, graph transformation, instruction scheduling, optimal scheduling
1	José R. Herrero, Juan J. Navarro	A Study on Load Imbalance in Parallel Hypermatrix Multiplication Using OpenMP.	PPAM	2005	DBLP DOI BibTeX RDF
1	Gordon Cichon, Pablo Robelly, Hendrik Seidel, Marcus Bronzel, Gerhard Fettweis	Compiler Scheduling for STA-Processors.	PARELEC	2004	DBLP DOI BibTeX RDF
1	Xiaotong Zhuang, Santosh Pande	Compiler Scheduling of Mobile Agents for Minimizing Overheads.	ICDCS	2003	DBLP DOI BibTeX RDF
1	Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke	Systematic Register Bypass Customization for Application-Specific Processors.	ASAP	2003	DBLP DOI BibTeX RDF
1	K. Subramani	An Analysis of Zero-Clairvoyant Scheduling.	TACAS	2002	DBLP DOI BibTeX RDF
1	Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil D. Dutt, Alexandru Nicolau	EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability.	DATE	1999	DBLP DOI BibTeX RDF