Search results for "computer architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Marco Platzner, Bernhard Rinner, Reinhold Weiss	A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs.	PDP	1995	DBLP DOI BibTeX RDF	distributed computer architecture, multi-DSP, application-specific computer architecture, constraint-check-function, performance, FPGAs, parallel architectures, computer architecture, digital simulation, hardware design, special purpose computers, design strategies, qualitative simulation
4	Sandro Neves Soares, Flávio Rech Wagner	From classroom to research: providing different services for computer architecture education.	WCAE	2007	DBLP DOI BibTeX RDF	computer architecture education, processor modeling and simulation
4	Timothy Daryl Stanley, George Embrey, Daniel Prigmore, Leslie D. Fife, Scott Mikolyski, Don Colton	Pedagogic value in understanding computer architecture of implementing the marie computer from null and lobur in the logic emulation software, multimedia logic.	WCAE	2007	DBLP DOI BibTeX RDF	education, computer architecture, microprocessor design, logic emulation
4	Alicia Asín Pérez, Darío Suárez Gracia, Víctor Viñals Yúfera	A proposal to introduce power and energy notions in computer architecture laboratories.	WCAE	2007	DBLP DOI BibTeX RDF	education, measurements, computer architecture, power, energy, platform, processor
4	David C. Roberts	A Specialized Computer Architecture for Text Retrieval.	Computer Architecture for Non-Numeric Processing	1978	DBLP DOI BibTeX RDF
3	William J. Dally	Moving the needle, computer architecture research in academe and industry.	ISCA	2010	DBLP DOI BibTeX RDF	research
3	Toktam Taghavi, Mark Thompson, Andy D. Pimentel	Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration.	SAMOS	2009	DBLP DOI BibTeX RDF	Computer architecture simulation, coordination, design space exploration, multiple views, linked views, exploratory visualization
3	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
3	Sarita V. Adve, David Brooks, Craig B. Zilles	Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007.	IEEE Micro	2008	DBLP DOI BibTeX RDF	Top Picks, reliability, computer architecture, transactional memory, variability, on-chip interconnects, compiler-architecture interactions, memory system design
3	Francisco Corbera, Eladio Gutiérrez, Julián Ramos, Sergio Romero, María A. Trenas	Development of a new MOODLE module for a basic course on computer architecture.	ITiCSE	2008	DBLP DOI BibTeX RDF	computer architecture, LMS, Moodle, automatic assessment
3	Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy K. John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson	Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education.	CollaborateCom	2008	DBLP DOI BibTeX RDF	simulation, Grid computing, virtualization, computer architecture, collaborative environments
3	Mohit Gambhir, Edward F. Gehringer, Yan Solihin	Animations of important concepts in parallel computer architecture.	WCAE	2007	DBLP DOI BibTeX RDF
3	Timothy Urness	Teaching computer organization/architecture by building a computer.	WCAE	2007	DBLP DOI BibTeX RDF	computer science education, computer architecture, hardware
3	Milos Becvár, Stanislav Kahánek	VLIW-DLX simulator for educational purposes.	WCAE	2007	DBLP DOI BibTeX RDF	simulation, education, computer architecture, VLIW
3	Chang-Burm Cho, Tao Li	Using Wavelet Domain Workload Execution Characteristics to Improve Accuracy, Scalability and Robustness in Program Phase Analysis.	ISPASS	2007	DBLP DOI BibTeX RDF	program execution variability, workload execution statistics, program phase analysis, computer architecture design, computer architecture optimization, program execution statistics, SPEC CPU 2000 benchmark, wavelet domain phase analysis, runtime workload execution characteristics, scalable phase analysis, sampled workload statistics, phase classification accuracy, wavelet transform, time domain, wavelet denoising
3	Timothy Sherwood, Joshua J. Yi	Guest Editors' Introduction: Computer Architecture Simulation and Modeling.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Computer Architecture simulation and modeling, IEEE Micro March-April 2006
3	Roland N. Ibbett, Juan Carlos Diaz y Carballo, D. A. W. Dolman	Computer architecture simulation models.	ITiCSE	2006	DBLP DOI BibTeX RDF	computer architecture simulation
3	Tilak Agerwala, Siddhartha Chatterjee	Computer Architecture: Challenges and Opportunities for the Next Decade.	IEEE Micro	2005	DBLP DOI BibTeX RDF	system-level power management, application, Computer architecture, workloads, accelerators, system performance, scale-out, power-aware architecture
3	Cecile Yehezkel, Mordechai Ben-Ari, Tommy Dreyfus	Computer architecture and mental models.	SIGCSE	2005	DBLP DOI BibTeX RDF	computer architecture education, visualization, mental models
3	Daniel Citron	MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
3	Ewa Z. Bem, Luke Petelczyc	MiniMIPS: a simulation project for the computer architecture laboratory.	SIGCSE	2003	DBLP DOI BibTeX RDF	simulation in lab environments, computer architecture
3	Ronald Moore, Bernd Klauer, Klaus Waldschmidt	What computer architecture can learn from computational intelligence-and vice versa.	EUROMICRO	1997	DBLP DOI BibTeX RDF	von Neumann model, neural network, parallelism, artificial intelligence, computer architecture, regularity, parallelizing compilers, granularity, data distribution, computational intelligence, multithreaded architecture
3	Herbert Grünbacher, Maziar Khosravipour	WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture.	ECBS	1996	DBLP DOI BibTeX RDF	teaching computer architecture, teaching computer organisation, teaching pipelining, DLX architecture, pipeline visualisation, WinDLX, MIPSim, ECBS
3	Timothy J. Stanley, Trevor N. Mudge	Systematic objective-driven computer architecture optimization.	ARVLSI	1995	DBLP DOI BibTeX RDF	objective-driven optimization, microarchitectural configuration, directed search problem, genetic algorithms, genetic algorithm, CAD, computer-aided design, computer architecture, computer architecture, memory hierarchy, search problems, memory architecture, dimensionality
3	D. K. Arvind, Robert D. Mullins, Vinod E. F. Rebello	Micronets: a model for decentralising control in asynchronous processor architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency
3	Arturo I. Concepcion	A Hierarchical Computer Architecture for Distributed Simulation.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	hierarchical computer architecture, modular discrete-event models, hierarchical multibus multiprocessor architecture, distributed processing, computer architecture, multiprocessing systems, distributed simulation
3	Manuel L. Anido, D. J. Allerton, Ed Zaluska	A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine.	ISCA	1989	DBLP DOI BibTeX RDF	Computer Image Generation, Computer Architecture, VLSI Design, Interprocessor Communication, RISC, Reduced Instruction Set Computers
3	Philip C. Treleaven, Richard P. Hopkins	A recursive computer architecture for VLSI.	ISCA	1982	DBLP DOI BibTeX RDF
3	Yaohan Chu	Direct Execution In A High-Level Computer Architecture.	ACM Annual Conference	1978	DBLP DOI BibTeX RDF	Control processor, Data processor, Lexical processing, Computer architecture, Interactive system, High-level architecture, Associative memory, Direct execution
2	Trevor N. Mudge	Guest Editor's Introduction: Top Picks from the Computer Architecture Conferences of 2009.	IEEE Micro	2010	DBLP DOI BibTeX RDF	Top Picks, multiprocessors, computer architecture, memory architecture
2	Zhigang Gao, Ganggang Xue, Guojun Dai, Xuehui Wei	Applying Two New Methods to the Teaching of Computer Architecture.	CIT	2010	DBLP DOI BibTeX RDF	Example Method, Extension Method, undergraduate teaching, Computer Architecture, computer education
2	Klaus Hildebrandt, Igor Podebrad, Bernd Klauer	A Computer Architecture with Hardwarebased Malware Detection.	ARES	2010	DBLP DOI BibTeX RDF	secure computer architecture, hardware based security, multicore, malware
2	Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi	A dynamically configurable coprocessor for convolutional neural networks.	ISCA	2010	DBLP DOI BibTeX RDF	dynamic reconfiguration, parallel computer architecture, convolutional neural networks
2	John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Cohesion: a hybrid memory model for accelerators.	ISCA	2010	DBLP DOI BibTeX RDF	computer architecture, cache coherence, accelerator
2	Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John	The virtual write queue: coordinating DRAM and last-level cache policies.	ISCA	2010	DBLP DOI BibTeX RDF	cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
2	Jean-Luc Gaudiot	Introducing the New Editor-in-Chief of IEEE Computer Architecture Letters.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF
2	C. Barnes, P. Vaidya, J. J. Lee	An XML-Based ADL Framework for Automatic Generation of Multithreaded Computer Architecture Simulators.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF
2	Timothy Daryl Stanley	Using digital logic simulation as a teaching aid in discrete mathematics, hardware and operating systems, networking, computer organization and computer architecture: a workshop outline.	SIGITE Conference	2009	DBLP DOI BibTeX RDF	visualization, learning environment, logic simulation
2	Igor Podebrad, Klaus Hildebrandt, Bernd Klauer	List of Criteria for a Secure Computer Architecture.	SECURWARE	2009	DBLP DOI BibTeX RDF	parts of von-Neumann- Maschine, computer-architecture, IT-security
2	Carlos Alario-Hoyos, Eduardo Gómez-Sánchez, Miguel L. Bote-Lorenzo, Guillermo Vega-Gorgojo, Juan I. Asensio-Pérez	Grid Service-Based Benchmarking Tool for Computer Architecture Courses.	EC-TEL	2009	DBLP DOI BibTeX RDF	service-oriented grid, education, architecture, Benchmarking
2	John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	Rigel: an architecture and scalable programming interface for a 1000-core accelerator.	ISCA	2009	DBLP DOI BibTeX RDF	low-level programming interface, computer architecture, accelerator
2	Aleksandar Ilic, Frederico Pratas, Leonel Sousa	Distributed Web-based Platform for Computer Architecture Simulation.	ISPDC	2008	DBLP DOI BibTeX RDF
2	ElMoustapha Ould-Ahmed-Vall, James Woodlee, Charles Yount, Kshitij A. Doshi, Seth Abraham	Using Model Trees for Computer Architecture Performance Analysis of Software Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	superscalar machine, computer architecture performance analysis, tuning software, statistical regression modeling, M5' algorithm, SPEC CPU2006 suite, performance model tree, prefetching, software application
2	Xuejun Liang	A Survey of Hands-on Assignments and Projects in Undergraduate Computer Architecture Courses.	SCSS	2007	DBLP DOI BibTeX RDF
2	Yoshiro Imai, Keiichi Kaneko, Masaki Nakagawa	A Web-based Visual Simulator with Communication Support and its Application to Computer Architecture Education.	ICALT	2007	DBLP DOI BibTeX RDF
2	Aashish Phansalkar, Ajay Joshi, Lizy Kurian John	Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite.	ISCA	2007	DBLP DOI BibTeX RDF	microprocessor performance counters, clustering, benchmark, SPEC
2	Zhenghong Wang, Ruby B. Lee	New cache designs for thwarting software cache-based side channel attacks.	ISCA	2007	DBLP DOI BibTeX RDF	security, cache, computer architecture, processor, timing attacks, side channel
2	Eric Chi, Stephen A. Lyon, Margaret Martonosi	Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits.	ISCA	2007	DBLP DOI BibTeX RDF	architecture, quantum
2	Umakishore Ramachandran, William D. Leahy Jr.	An integrated approach to teaching computer systems architecture.	WCAE	2007	DBLP DOI BibTeX RDF
2	Guillermo Payá Vayá, Thomas Jambor, Konstantin Septinus, Sebastian Hesselbarth, Holger Flatt, Marc Freisfeld, Peter Pirsch	ChipDesign: from theory to real world.	WCAE	2007	DBLP DOI BibTeX RDF	computer architecture education, integrated circuits
2	David H. Albonesi	Productive and Healthy Debate.	IEEE Micro	2007	DBLP DOI BibTeX RDF	single-threaded, security, reliability, low power, computer architecture, multithreaded, debates
2	Richard Mateosian	Looking Back.	IEEE Micro	2007	DBLP DOI BibTeX RDF	computers and consciousness, usability, project management, programming, computer architecture, Windows, review, globalization, books
2	Eduard Ayguadé, Wolfgang Karl, Koen De Bosschere, Jean-Francois Collard	Topic 7: Parallel Computer Architecture and Instruction Level Parallelism.	Euro-Par	2006	DBLP DOI BibTeX RDF
2	Yale N. Patt	Computer Architecture Research and Future Microprocessors: Where Do We Go from Here?	ISCA	2006	DBLP DOI BibTeX RDF
2	Isabel Pedrosa, António José Mendes, Mário Zenha Rela	edu.LMC and Other LMC Simulation Approaches: Contributions to Computer Architecture Education Using the LMC Paradigm.	Education for the 21st Century	2006	DBLP DOI BibTeX RDF
2	Chenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, Yan Solihin	Improving Cost, Performance, and Security of Memory Encryption and Authentication.	ISCA	2006	DBLP DOI BibTeX RDF
2	Salvador Petit, Noel Tomás, Julio Sahuquillo, Ana Pont	An execution-driven simulation tool for teaching cache memories in introductory computer organization courses.	WCAE	2006	DBLP DOI BibTeX RDF
2	L. S. K. Udugama, Janath C. Geeganage	Students' experimental processor: a processor integrated with different types of architectures for educational purposes.	WCAE	2006	DBLP DOI BibTeX RDF
2	James Donald, Margaret Martonosi	An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation.	Computer Architecture Letters	2006	DBLP DOI BibTeX RDF
2	Xiaofeng Gao, Allan Snavely, Larry Carter	Path Grammar Guided Trace Compression and Trace Approximation.	HPDC	2006	DBLP DOI BibTeX RDF	path grammar guided trace compression, trace approximation, PGGTC, Sequitur algorithm, selective dumping, memory signature, parallel computer, computer architecture, parallel machine, trace-driven simulation, cache storage
2	Joshua J. Yi, David J. Lilja	Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Simulation, modeling, evaluation, measurement, modeling techniques, measurement techniques, modeling of computer architecture, simulation of multiple-processor systems
2	Yongsu Park, Yong Ho Song, Eul-Gyu Im	Design of a Reliable Hardware Stack to Defend Against Frame Pointer Overwrite Attacks.	ISI	2006	DBLP DOI BibTeX RDF	computer architecture, computer security, buffer overflow attack
2	Yongsu Park, Younho Lee, Heeyoul Kim, Gil-Joo Lee, Il-Hee Kim	Hardware Stack Design: Towards an Effective Defence Against Frame Pointer Overwrite Attacks.	IWSEC	2006	DBLP DOI BibTeX RDF	computer architecture, computer security, buffer overflow attack
2	Joshua J. Yi, David J. Lilja, Douglas M. Hawkins	Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	simulation output analysis, measurement techniques, Performance analysis and design aids
2	Yanwei Niu, Ziang Hu, Kenneth E. Barner, Guang R. Gao	Performance Modelling and Optimization of Memory Access on Cellular Computer Architecture Cyclops64.	NPC	2005	DBLP DOI BibTeX RDF
2	Theo Ungerer, Josep-Lluis Larriba-Pey, Kevin Skadron, Pedro Trancoso	Topic 7 - Parallel Computer Architecture and ILP.	Euro-Par	2005	DBLP DOI BibTeX RDF
2	Eric McCorkle	Programmable bus/memory controllers in modern computer architecture.	ACM Southeast Regional Conference	2005	DBLP DOI BibTeX RDF
2	Wen-mei W. Hwu, Sanjay J. Patel	The Future of Computer Architecture Research: An Industrial Perspective.	HPCA	2005	DBLP BibTeX RDF
2	Kaushal Sanghai, Ting Su, Jennifer G. Dy, David R. Kaeli	A multinomial clustering model for fast simulation of computer architecture designs.	KDD	2005	DBLP DOI BibTeX RDF	mixture of multinomials, simulation, clustering, k-means, EM, program phase
2	Mark Thorson	Internet Nuggets.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
2	Mark Thorson	Internet nuggets.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF	Internet, Internet
2	Magnus Ekman, Fredrik Warg, Jim Nilsson	An in-depth look at computer performance growth.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
2	Mark Thorson	Internet nuggets.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
2	Pedro D. Medeiros, Vítor Duarte, Maria Cecilia Gomes, Rui F. Marques	Using a PC simulator to illustrate input-output programming techniques.	ITiCSE	2005	DBLP DOI BibTeX RDF	virtual machine, computer architecture, teaching, input output programming
2	James Fung, Steve Mann	OpenVIDIA: parallel GPU computer vision.	ACM Multimedia	2005	DBLP DOI BibTeX RDF	chirplet transform, hardware accelerated computer vision, openVIDIA, computer vision, computer graphics, GPU, computer architecture, radon transform, mediated reality
2	Soong Hyun Shin, Cheol Hong Kim, Chu Shik Jhon	An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information.	EUC	2005	DBLP DOI BibTeX RDF	Computer architecture, embedded processor, instruction cache, cache prefetching
2	Doug Burger, Anand Sivasubramaniam	Tools for computer architecture research.	SIGMETRICS Performance Evaluation Review	2004	DBLP DOI BibTeX RDF
2	Thomas L. Sterling	Towards Memory Oriented Scalable Computer Architecture and High Efficiency Petaflops Computing.	NPC	2004	DBLP DOI BibTeX RDF
2	Kemal Ebcioglu, Wolfgang Karl, André Seznec, Marco Aldinucci	Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism.	Euro-Par	2004	DBLP DOI BibTeX RDF
2	Erik Larsson, Anders Larsson	Student-oriented examination in a computer architecture course.	ITiCSE	2004	DBLP DOI BibTeX RDF	indivudual learning process, learning, examination
2	Guillermo Vega-Gorgojo, Yannis A. Dimitriadis, Eduardo Gómez-Sánchez, Miguel L. Bote-Lorenzo	Learning Grid technologies in a project-based computer architecture course.	CCGRID	2004	DBLP DOI BibTeX RDF
2	Jong Whoa Na	A Parallel Optical Computer Architecture for Large Database and Knowledge Based Systems.	CIS	2004	DBLP DOI BibTeX RDF
2	Jong Whoa Na	A Parallel Electro-Optical Computer Architecture for Artificial Intelligence.	PDCAT	2004	DBLP DOI BibTeX RDF
2	Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas	iWatcher: Efficient Architectural Support for Software Debugging.	ISCA	2004	DBLP DOI BibTeX RDF
2	Mark Thorson	Internet nuggets.	SIGARCH Computer Architecture News	2004	DBLP DOI BibTeX RDF
2	Mark Thorson	Internet nuggets.	SIGARCH Computer Architecture News	2004	DBLP DOI BibTeX RDF
2	Cheol Hong Kim, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon	Adaptive Block Management for Victim Cache by Exploiting L1 Cache History Information.	EUC	2004	DBLP DOI BibTeX RDF	Block Management, Low Power, Computer Architecture, Victim Cache
2	Constantine Katsinis, Bahram Nabet	A Scalable Interconnection Network Architecture for Petaflops Computing.	The Journal of Supercomputing	2004	DBLP DOI BibTeX RDF	petaflops computing, performance analysis, interconnection networks, computer architecture
2	Michael A. Arbib	Towards a neurally-inspired computer architecture.	Natural Computing	2003	DBLP DOI BibTeX RDF	computer architecture, neural computing, cooperative computation
2	Anthony S. Fong	A computer architecture with access control and cache option tags on individual instruction operands.	SIGARCH Computer Architecture News	2003	DBLP DOI BibTeX RDF	operand descriptor, optional encaching, system attributes, access control, data coherency
2	Jean-Louis Lafitte	Qualitatively matching computer architecture with Turing machine.	SIGARCH Computer Architecture News	2003	DBLP DOI BibTeX RDF
2	Kevin Skadron, Margaret Martonosi, David I. August, Mark D. Hill, David J. Lilja, Vijay S. Pai	Challenges in Computer Architecture Evaluation.	IEEE Computer	2003	DBLP DOI BibTeX RDF
2	Mark Holland, James Harris, Scott Hauck	Harnessing FPGAs for Computer Architecture Education.	MSE	2003	DBLP DOI BibTeX RDF
2	Omid Mirmotahari, Christian Holmboe, Jens Kaasbøll	Difficulties learning computer architecture.	ITiCSE	2003	DBLP DOI BibTeX RDF	assembler programming, Boolean algebra, abstraction level
2	Benjoe A. Juliano, Chi-Hui Chen, Elena Kroumova	Observations from using two modes of teaching undergraduate computer architecture.	ITiCSE	2003	DBLP DOI BibTeX RDF	evaluating learning and teaching, online course delivery and management, web-based learning, teaching methods, teaching materials
2	Joshua J. Yi, David J. Lilja, Douglas M. Hawkins	A Statistically Rigorous Approach for Improving Simulation Methodology.	HPCA	2003	DBLP DOI BibTeX RDF
2	Mok Pak Lun, Richard Li, Anthony S. Fong	Method manipulation in an object-oriented processor.	SIGARCH Computer Architecture News	2003	DBLP DOI BibTeX RDF
2	Edward F. Gehringer	A pair-programming experiment in a non-programming course.	OOPSLA Companion	2003	DBLP DOI BibTeX RDF	laboratory exercises, computer architecture, pair programming
2	Linda Null, Julia Lobur	MarieSim: The MARIE computer simulator.	ACM Journal of Educational Resources in Computing	2003	DBLP DOI BibTeX RDF	Computer architecture simulator, introductory architecture, education
2	Harold W. Lawson	The Datasaab Flexible Central Processing Unit.	History of Nordic Computing	2003	DBLP DOI BibTeX RDF	hardware-software tradeoffs, Computer architecture, microprogramming, computer history