Search results for "configurable logic blocks"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	configurable logic blocks, fault diagnosis, BIST, FPGA testing
2	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
2	K. K. Lee, D. F. Wong	An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs.	ICCD	1999	DBLP DOI BibTeX RDF
2	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.	ITC	1998	DBLP DOI BibTeX RDF	IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase
1	Mohammed Y. Niamat, Tejas Raviraj, Sowmya Panuganti, Srinivasa Vemuru	Quantum-Dot Cellular Automata Implementation of FPGA Configurable Logic Blocks.	CDES	2010	DBLP BibTeX RDF
1	Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Châtelet	A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks.	DDECS	2010	DBLP DOI BibTeX RDF
1	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
1	Yajun Ran, Malgorzata Marek-Sadowska	Designing via-configurable logic blocks for regular fabric.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Marvin Tom, David Leong, Guy G. Lemieux	Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
1	Pongstorn Maidee, Kia Bazargan	Defect-Tolerant FPGA Architecture Exploration.	FPL	2006	DBLP DOI BibTeX RDF
1	P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis	A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis	Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Lei Cheng, Martin D. F. Wong	Floorplan Design for Multimillion Gate FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.	ISLPED	2005	DBLP DOI BibTeX RDF	activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing
1	Kuan Zhou, John F. McDonald	Multi-GHz SiGe design methodologies for reconfigurable computing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CLB, virtex, FPGA, SiGe
1	Mohammed Y. Niamat, Surya S. Hejeebu, M. Alam	A BIST Approach for Testing FPGAs Using JBITS.	FCCM	2005	DBLP DOI BibTeX RDF
1	Juan Antonio Carballo, Kevin J. Nowka, Seung-Moon Yoo, Ivan Vo, Clay Cranford, V. Robert Norman	Requirement-based design methods for adaptive communications links.	DAC	2004	DBLP DOI BibTeX RDF	communication architectures, energy efficient design
1	Paul Kohlbrenner, Kris Gaj	An embedded true random number generator for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	TRNG, FPGA, random numbers, RNG, cryptographic
1	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage
1	Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi	Exploring Logic Block Granularity for Regular Fabrics.	DATE	2004	DBLP DOI BibTeX RDF
1	Mahmoud Meribout, Masato Motomura	A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Dynamic reconfigurable logic, scheduling, partitioning, allocation, communication cost
1	Mahmoud Meribout, Masato Motomura	Efficient metrics and high-level synthesis for dynamically reconfigurable logic.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Seok-Bum Ko, Jien-Chung Lo	Efficient Realization of Parity Prediction Functions in FPGAs.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	parity prediciton functions, Davio''s expansion, AND/XOR expressions, FPGA, technology mapping
1	Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald, Russell P. Kraft, Bryan S. Goda	A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.	FPGA	2003	DBLP DOI BibTeX RDF
1	Ilias Tagkopoulos, Charles A. Zukowski, German Cavelier, Dimitris Anastassiou	A custom FPGA for the simulation of gene regulatory networks.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	custom mixed signal FPGA, genetic pathways, gene regulatory networks
1	Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis	FPGA Architecture Design and Toolset for Logic Implementation.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee	Accurate Area and Delay Estimators for FPGAs.	DATE	2002	DBLP DOI BibTeX RDF
1	J. M. Pierre Langlois, Dhamin Al-Khalili	Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Yousuke Nakamura, Kei Hiraki	Highly Fault-Tolerant FPGA Processor by Degrading Strategy.	PRDC	2002	DBLP DOI BibTeX RDF
1	Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. M. Ferreira	On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
1	J. M. Pierre Langlois, Dhamin Al-Khalili, Robert J. Inkol	Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation.	VLSI Signal Processing	2002	DBLP DOI BibTeX RDF	quadrature demodulation, digital down conversion, polyphase filtering, field programmable gate arrays, digital filtering
1	Wei-Je Huang, Edward J. McCluskey	A memory coherence technique for online transient error recovery of FPGA configurations.	FPGA	2001	DBLP DOI BibTeX RDF	fault tolerance, FPGA, error recovery, memory coherence
1	Reiner W. Hartenstein	Reconfigurable Computing: A New Business Model and its Impact on SoC Design.	DSD	2001	DBLP DOI BibTeX RDF
1	W. Shi, K. Kumar, Fabrizio Lombardi	On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips. (PDF / PS)	DFT	2000	DBLP DOI BibTeX RDF
1	Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley	Reconfigurable Array Media Processor (RAMP).	FCCM	2000	DBLP DOI BibTeX RDF
1	Joachim Pistorius, Edmée Legai, Michel Minoux	PartGen: a generator of very large circuits to benchmark thepartitioning of FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Valery Sklyarov	Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	Testing the Logic Cells and Interconnect Resources for FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Satoshi Kaneko, Hideo Ito	Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF
1	C. K. Chung, Philip Heng Wai Leong	An Architecture for Solving Boolean Satisfiability Using Runtime Configurable Hardware. (PDF / PS)	ICPP Workshops	1999	DBLP DOI BibTeX RDF
1	Riku Uusikartano, Jarkko Niittylahti, Markku Renfors	Area-optimized FPGA implementation of a digital FM modulator.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Philip Heng Wai Leong, P. K. Tsang, T. K. Lee	A FPGA Based Forth Microprocessor.	FCCM	1998	DBLP DOI BibTeX RDF
1	Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara	Universal Fault Diagnosis for Lookup Table FPGAs.	IEEE Design & Test of Computers	1998	DBLP DOI BibTeX RDF
1	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian	Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	FPGA, VLSI, Test, CMOS, IC
1	Martine D. F. Schlag, Pak K. Chan, Jackson Kong	Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF