Search results for "control logic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Jacob Savir	Random pattern testability of memory control logic.	VTS	1997	DBLP DOI BibTeX RDF	embedded memory control logic, exposure probability, fault detection, integrated memory circuits, signal probability, random pattern testability
2	Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González	End-to-end register data-flow continuous self-test.	ISCA	2009	DBLP DOI BibTeX RDF	end-to-end protection, online testing, degradation, design errors, control logic
2	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche	Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.	European Test Symposium	2008	DBLP DOI BibTeX RDF	microprocessor, error detecting codes, on-line testing, control logic
2	Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche	A low-cost concurrent error detection technique for processor control logic.	DATE	2008	DBLP DOI BibTeX RDF
2	Christoph Sünder, Monika Wenger, Christian Hanni, Ivo Gosetti, Heinrich Steininger, Josef Fritsche	Transformation of existing IEC 61131-3 automation projects into control logic according to IEC 61499.	ETFA	2008	DBLP DOI BibTeX RDF
2	Kwan Hee Han, Jun Woo Park	Development of Object-Oriented Modeling Tool for the Design of Industrial Control Logic.	SERA	2007	DBLP DOI BibTeX RDF
2	T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani	SEU Mitigation Techniques for Microprocessor Control Logic.	EDCC	2006	DBLP DOI BibTeX RDF
2	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry.	SLIP	2005	DBLP DOI BibTeX RDF	wire-length distribution model, routing, interconnect, rent
2	Hashem Hashemi Najaf-abadi	A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Kerstin Eder, Geoff Barrett	Achieving maximum performance: a method for the verification of interlocked pipeline control logic.	DAC	2002	DBLP DOI BibTeX RDF	interlock logic, pipeline stall, verification
2	Yoshitomo Ikkai, Kazuhisa Ikeda, Norihisa Komoda, Akira Yamane, Isao Tone	Sequential Control Logic Inferring Method from Observed Plant I/O Data.	IDA	1999	DBLP DOI BibTeX RDF
2	Jeffrey L. Burns, Jack A. Feldman	C5M-a control-logic layout synthesis system for high-performance microprocessors.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee	Eliminating False Loops Caused by Sharing in Control Path. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF	false loops, control path sharing, timing validation, design sign-off phase, data path sharing, control logic sharing, removal algorithm, computation complexity, high level synthesis, high level synthesis, filter, resource sharing, logic minimization
2	Jin Li, Chuan-lin Wu	A novel architecture for an ATM switch. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	multicast function, shared-buffer ATM switch, first-in and first-out shared buffer, FIFO address queue, cell-loss performance, performance evaluation, asynchronous transfer mode, ATM switch, B-ISDN, control logic, buffer utilization
2	Gernot Richter, Bruno Maffeo	Toward a Rigorous Interpretation of ESML-Extended Systems Modeling Language.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	translation principles, rigorous interpretation, ESML, extended systems modeling language, graphics-based language, data flow diagram notation, transformation schema, token game, real-time systems, real-time systems, Petri nets, Petri nets, systems analysis, visual languages, control logic
2	Christine M. Gerveshi	Comparison of CMOS PLA and polycell representations of control logic.	DAC	1986	DBLP DOI BibTeX RDF
1	Yevgeny Gerlits, Alexey V. Khoroshilov	Model-Based Testing of Safety Critical Real-Time Control Logic Software	MBT	2012	DBLP DOI BibTeX RDF
1	Grzegorz J. Nalepa, Blazej Biesiada	Declarative Design of Control Logic for Mindstorms NXT with XTT2 Method.	ICCCI	2011	DBLP DOI BibTeX RDF
1	Muthukumaran Chandrasekaran, Karthik Nadig, Khaled Rasheed	Evolving Efficient Sensor Arrangement and Obstacle Avoidance Control Logic for a Miniature Robot.	IEA/AIE	2011	DBLP DOI BibTeX RDF
1	Sebastian Offermann, Robert Wille, Rolf Drechsler	Efficient realization of control logic in reversible circuits.	FDL	2011	DBLP BibTeX RDF
1	Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer	Exponent monitoring for low-cost concurrent error detection in FPU control logic.	VTS	2011	DBLP DOI BibTeX RDF
1	Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González	Implementing End-to-End Register Data-Flow Continuous Self-Test.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	end-to-end protection, Online testing, degradation, design errors, control logic
1	Abbas Dideban, Hassane Alla	Feedback control logic synthesis for non safe Petri nets	CoRR	2010	DBLP BibTeX RDF
1	Oscar Ljungkrantz, Knut Åkesson, Martin Fabian, Chengyin Yuan	Formal Specification and Verification of Industrial Control Logic Components.	IEEE T. Automation Science and Engineering	2010	DBLP DOI BibTeX RDF
1	Valerio Genovese, Daniele Rispoli, Dov M. Gabbay, Leendert W. N. van der Torre	Modal Access Control Logic - Axiomatization, Semantics and FOL Theorem Proving.	STAIRS	2010	DBLP DOI BibTeX RDF
1	Richard Phillips, Bonnie Montalvo	Using emulation to debug control logic code.	Winter Simulation Conference	2010	DBLP DOI BibTeX RDF
1	Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche	Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	microprocessor, on-line testing, control logic
1	Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella	Microarchitectural Online Testing for Failure Detection in Memory Order Buffers.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	memory order buffer, error detection, soft errors, microarchitecture, defects, Online testing, control logic
1	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
1	Leonid Ryzhyk, Yanjin Zhu, Gernot Heiser	The case for active device drivers.	ApSys	2010	DBLP DOI BibTeX RDF	stack ripping, concurrency, device drivers
1	Abbas Dideban, Hassane Alla	Feedback control logic synthesis for non safe Petri nets	CoRR	2009	DBLP BibTeX RDF
1	Kristofer Bengtsson, Bengt Lennartson, Chengyin Yuan, Petter Falkman, Stephan Biller	Operation-oriented specification for integrated control logic development.	CASE	2009	DBLP DOI BibTeX RDF
1	Xiaoqing Zeng, Qipeng Xiong, Decun Dong, Jingjing Guo	Development of Fatigue Driving Detection Method Based on Fuzzy Control Logic.	ISCID	2009	DBLP DOI BibTeX RDF
1	Jesús A. Trujillo, Pawel Pawlewski, Zbigniew J. Pasek	Reference Traces by Simulation for Tracking Control-logic.	ETFA	2009	DBLP DOI BibTeX RDF
1	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
1	Yin Wang, Stéphane Lafortune, Terence Kelly, Manjunath Kudlur, Scott A. Mahlke	The theory of deadlock avoidance via discrete control.	POPL	2009	DBLP DOI BibTeX RDF	discrete control theory, dynamic deadlock avoidance, parallel programming, concurrent programming, multicore processors, multithreaded programming
1	Vipul Mathur, Sanket Dhopeshwarkar, Varsha Apte	MASTH proxy: an extensible platform for web overload control.	WWW	2009	DBLP DOI BibTeX RDF	admission control, web server, proxy, overload, multi-class
1	Markus Püschel, Peter A. Milder, James C. Hoe	Permuting streaming data using RAMs.	J. ACM	2009	DBLP DOI BibTeX RDF	data reordering, linear bit mapping, streaming datapath, stride permutation, Permutation, switch, RAM, connection network, matrix transposition
1	Chris Wynnyk, Malik Magdon-Ismail	Pricing the American Option Using Reconfigurable Hardware.	CSE	2009	DBLP DOI BibTeX RDF
1	A. Lehmann, T. Eichelmann, U. Trick, Rolf Lasch, Björn Ricks, Ralf Tönjes	TeamCom: A Service Creation Platform for Next Generation Networks.	ICIW	2009	DBLP DOI BibTeX RDF
1	Christos Kloukinas	Better abstractions for reusable components & architectures.	ICSE Companion	2009	DBLP DOI BibTeX RDF
1	Jean-Yves Tourneret, Neil J. Bershad, José Carlos M. Bermudez	Echo Cancellation - The Generalized Likelihood Ratio Test For Double-Talk Versus Channel Change.	IEEE Transactions on Signal Processing	2009	DBLP DOI BibTeX RDF
1	Do-Hyeon Kim, Kwang-Baek Kim, Eui-Young Cha	Fuzzy truck control scheme for obstacle avoidance.	Neural Computing and Applications	2009	DBLP DOI BibTeX RDF	Fuzzy truck, Truck backer-upper, Fuzzy control, Obstacle avoidance
1	Francisco P. Maturana, Dan L. Carnahan, Kenwood H. Hall	Distributed Agent Software for Automation.	Handbook of Automation	2009	DBLP DOI BibTeX RDF
1	Yaochu Jin, Bernhard Sendhoff	Fuzzy Logic in Evolving in silicoOscillatory Dynamics for Gene Regulatory Networks.	Fuzzy Systems in Bioinformatics and Computational Biology	2009	DBLP DOI BibTeX RDF
1	Martín Abadi	Variations in Access Control Logic.	DEON	2008	DBLP DOI BibTeX RDF
1	David Sheldon, Frank Vahid	Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC
1	Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
1	David Sheldon, Frank Vahid	A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA
1	Umar Toseef, Asanga Udugama, Carmelita Görg, Changpeng Fan, Frank Pittmann	Realization of multiple access interface management and flow mobility in IPv6.	MOBILWARE	2008	DBLP DOI BibTeX RDF	flow management in IPv6, non-3GPP, optimized bandwidth resources usage, traffic filtering, 3GPP
1	Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti	Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.	DFT	2008	DBLP DOI BibTeX RDF
1	Enrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino	Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.	DSD	2008	DBLP DOI BibTeX RDF
1	Francisco P. Maturana, Dan L. Carnahan, Donald D. Theroux, Kenwood H. Hall	Distributed multi sensor agent for composite curing control.	ETFA	2008	DBLP DOI BibTeX RDF
1	Alessandro Vanelli-Coralli, Giovanni Emanuele Corazza, Claudio Palestini, Raffaella Pedone, Marco Villanti, Ho-Jin Lee, Pansoo Kim	Code Acquisition for Next Generation Mobile Broadband Satellite Services.	ICC	2008	DBLP DOI BibTeX RDF
1	Jian-hua Qiao, Lin-sheng Li, Jinggang Zhang	Design of Rail Surface Crack-detecting System Based on Linear CCD Sensor.	ICNSC	2008	DBLP DOI BibTeX RDF
1	Crispín Gómez Requena, María Engracia Gómez, Pedro Juan López Rodríguez, José Duato	An Efficient Switching Technique for NoCs with Reduced Buffer Requirements.	ICPADS	2008	DBLP DOI BibTeX RDF
1	Yves Le Traon, Tejeddine Mouelhi, Alexander Pretschner, Benoit Baudry	Test-Driven Assessment of Access Control in Legacy Applications.	ICST	2008	DBLP DOI BibTeX RDF
1	Rafal Dlugosz, Kris Iniewski	Power and area efficient circular-memory switched-capacitor FIR baseband filter for WCDMA/GSM.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Sang C. Park, Chang Mok Park, Gi-Nam Wang, Jonggeun Kwak, Sungjoo Yeo	PLCStudio: Simulation based PLC code verification.	Winter Simulation Conference	2008	DBLP DOI BibTeX RDF
1	Craig L. Robinson, P. R. Kumar	Optimizing controller location in networked control systems with packet drops.	IEEE Journal on Selected Areas in Communications	2008	DBLP DOI BibTeX RDF
1	Berk Sunar, Gunnar Gaubatz, Erkay Savas	Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Control Structure Reliability, Hardware, Testing and Fault-Tolerance
1	Charles C. Zhang, Marianne Winslett	Distributed Authorization by Multiparty Trust Negotiation.	ESORICS	2008	DBLP DOI BibTeX RDF
1	Crispín Gómez Requena, María Engracia Gómez, Pedro López, José Duato	Reducing Packet Dropping in a Bufferless NoC.	Euro-Par	2008	DBLP DOI BibTeX RDF
1	Marcos Paulo Mello Araujo, Nadia Nedjah, Luiza de Macedo Mourelle	Logic Synthesis for FSMs Using Quantum Inspired Evolution.	IDEAL	2008	DBLP DOI BibTeX RDF
1	Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah	Reveal: A Formal Verification Tool for Verilog Designs.	LPAR	2008	DBLP DOI BibTeX RDF
1	Nabil Schear, David R. Albrecht, Nikita Borisov	High-Speed Matching of Vulnerability Signatures.	RAID	2008	DBLP DOI BibTeX RDF
1	Paula Montoto, Alberto Pan, Juan Raposo, José Losada, Fernando Bellas, Javier López	A Workflow-Based Approach for Creating Complex Web Wrappers.	WISE	2008	DBLP DOI BibTeX RDF	data mining, web information systems, web automation, web wrappers
1	Jin Hwan Park, H. K. Dai	Reconfigurable hardware solution to parallel prefix computation.	The Journal of Supercomputing	2008	DBLP DOI BibTeX RDF	Parallel prefix computation, Field-programmable gate arrays, Pipeline, Dataflow, Reconfigurable hardware
1	Kazuyuki Kojima, Keiichi Watanuki	Automatic Generation of VHDL for Control Logic of Air Conditioning Using Evolutionary Computation.	JACIII	2007	DBLP BibTeX RDF
1	Jiuh-Biing Sheu	Microscopic modeling and control logic for incident-responsive automatic vehicle movements in single-automated-lane highway systems.	European Journal of Operational Research	2007	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Chico: An On-chip Hardware Checker for Pipeline Control Logic.	MTV	2007	DBLP DOI BibTeX RDF
1	Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji	Methodology for low power test pattern generation using activity threshold control logic.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Eric Schweikardt	Modular robotics as tools for design.	Creativity & Cognition	2007	DBLP DOI BibTeX RDF	design, education, toys, constructionism, modular robotics
1	Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz	Automated generation of layout and control for quantum circuits.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	ion trap, CAD, control, quantum computing, layout
1	Ilya Wagner, Valeria Bertacco	Engineering trust with semantic guardians.	DATE	2007	DBLP DOI BibTeX RDF
1	Bin Zhou, Yizheng Ye, Yongsheng Wang	Simultaneous reduction in test data volume and test time for TRC-reseeding.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	encoded vector, twisted-ring counter, built-in self test
1	Jean-Vincent Loddo, Luca Saiu	Status report: marionnet or "how to implement a virtual network laboratory in six months and be happy".	ML	2007	DBLP DOI BibTeX RDF	GUI, virtual machine, emulation, OCaml, static typing, user mode linux
1	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Impact of interconnect length changes on effective materials properties (dielectric constant).	SLIP	2007	DBLP DOI BibTeX RDF	performance, routing, interconnect, cycle time, interconnect model, rent, path delay
1	Juhani Heilala, Jari Montonen, Arttu Salmela, Pasi Järvenpää	Modeling and simulation for customer driven manufacturing system design and operations planning.	Winter Simulation Conference	2007	DBLP DOI BibTeX RDF
1	Wei Wang, Qiang Wu, Wei Xie	Hardware-Software Co-design for Dynamic Reconfigurable Computing with Collaborative Supports of Architecture and Operating System.	CSCWD	2007	DBLP DOI BibTeX RDF
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Automatic On-chip Memory Minimization for Data Reuse.	FCCM	2007	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton	Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications.	FPL	2007	DBLP DOI BibTeX RDF
1	Tim McComb, Luke Wildman	A Combined Approach for Information Flow Analysis in Fault Tolerant Hardware.	ICECCS	2007	DBLP DOI BibTeX RDF
1	Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko	A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Nigel Drego, Anantha Chandrakasan, Duane S. Boning	A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays.	ISQED	2007	DBLP DOI BibTeX RDF
1	Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan	Multi-Dimensional Circuit and Micro-Architecture Level Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Jun Nishiyama, Hiroyuki Sugahara, Tetsuya Okada, Takashi Kunifuji, Yamato Fukuta, Masayuki Matsumoto	A signal control system by optical LAN and design simplification.	SMC	2007	DBLP DOI BibTeX RDF
1	Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek	Automatic Design Space Exploration of Register Bypasses in Embedded Processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Gang Chen, Guoqiang Bai, Hongyi Chen	A New Systolic Architecture for Modular Division.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Modular division, computer arithmetic, public key cryptosystems, systolic architecture, hardware algorithm
1	Ling Zhuo, Viktor K. Prasanna	Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	computations on matrices, field-programmable gate arrays, parallel algorithms, Scientific computing, reconfigurable hardware
1	Holger Bock Axelsen, Robert Glück, Tetsuo Yokoyama	Reversible Machine Code and Its Abstract Processor Architecture.	CSR	2007	DBLP DOI BibTeX RDF
1	Ta-Hsiang Chung, Yi-Sheng Huang	Design of a Supervisor for Traffic Light Systems.	KES	2007	DBLP DOI BibTeX RDF	timed coloured Petri nets, signal timing plan, traffic control
1	Paolo Costa, Luca Mottola, Amy L. Murphy, Gian Pietro Picco	Programming Wireless Sensor Networks with the TeenyLimeMiddleware.	Middleware	2007	DBLP DOI BibTeX RDF	Wireless sensor and actuator networks, middleware, tuple spaces
1	Lei Feng, W. Murray Wonham, P. S. Thiagarajan	Designing communicating transaction processes by supervisory control theory.	Formal Methods in System Design	2007	DBLP DOI BibTeX RDF	Communicating transaction processes, Discrete-event systems, Supervisory control, Message sequence charts
1	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Shielding against design flaws with field repairable control logic.	DAC	2006	DBLP DOI BibTeX RDF	hardware patching, processor verification
1	Fuyuki Ishikawa, Nobukazu Yoshioka, Shinichi Honiden	Service-oriented and autonomous distribution and provision of multimedia contents.	AAMAS	2006	DBLP DOI BibTeX RDF	multimedia, mobile agents, service-oriented computing, agreement, agent framework
1	Neil C. Audsley, Michael Ward	Syntax-driven implementation of software programming language control constructs and expressions on FPGAs.	CASES	2006	DBLP DOI BibTeX RDF	fpga, compilation, language
1	Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda	Rapid estimation of control delay from high-level specifications.	DAC	2006	DBLP DOI BibTeX RDF	control delay, high level synthesis, estimation, FSM