Search results for "coupling capacitance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan	Global interconnect sizing and spacing with consideration of coupling capacitance.	ICCAD	1997	DBLP DOI BibTeX RDF	GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
2	Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury	Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew.	DAC	2007	DBLP DOI BibTeX RDF
2	Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury	Delay and Clock Skew Variation due to Coupling Capacitance and Inductance.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong	An ECO routing algorithm for eliminating coupling-capacitance violations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong	Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.	ISQED	2005	DBLP DOI BibTeX RDF	Layer migration, Max-cut, Capacitance coupling
2	Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra	Timing driven track routing considering coupling capacitance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Li Ding 0002, Pinaki Mazumder, David Blaauw	Crosstalk noise estimation using effective coupling capacitance.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai	An On-Chip Coupling Capacitance Measurement Technique.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Youxin Gao, D. F. Wong	Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model.	ASP-DAC	1999	DBLP DOI BibTeX RDF
1	Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang	Density gradient minimization with coupling-constrained dummy fill for CMP control.	ISPD	2010	DBLP DOI BibTeX RDF	density gradient, manufacturability, chemical-mechanical polishing, dummy fill
1	Mingjing Chen, Alex Orailoglu	Deflecting crosstalk by routing reconsideration through refined signal correlation estimation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	signal correlation, routing, crosstalk
1	Ge Chen, Saeid Nooshabadi, Steven G. Duvall	An optimization strategy for low energy and high performance for the on-chip interconnect signalling.	ISLPED	2009	DBLP DOI BibTeX RDF	interconnect signaling, low energy
1	Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam	Variation-aware multimetric optimization during gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise
1	Ahmad Sinjari, Sazzadur Chowdhury	A Single-Pole-Triple-Throw (SP3T) MEMS RF switch for 24 GHz short range radar.	EIT	2009	DBLP DOI BibTeX RDF
1	Hariharan Sankaran, Srinivas Katkoori	On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs.	ISQED	2009	DBLP DOI BibTeX RDF
1	Kunal P. Ganeshpure, Sandip Kundu	An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu	Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Jae-Seok Yang, David Z. Pan	Overlay aware interconnect and timing variation modeling for double patterning technology.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng	Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction.	ISPD	2008	DBLP DOI BibTeX RDF	crosstalk reduction, full-chip routing, gridless routing, implicit connection graph-based router, non-slicing floorplanning, detailed routing
1	Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang	A noniterative equivalent waveform model for timing analysis in presence of crosstalk.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	equivalent waveform, delay, noise, timing analysis, Deep sub micron
1	Fu-Wei Chen, Yi-Yu Liu	Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.	DATE	2008	DBLP DOI BibTeX RDF
1	Jae-Seok Yang, Andrew R. Neureuther	Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner.	ISQED	2008	DBLP DOI BibTeX RDF	worst corner, noise, crosstalk, variation, signal integrity
1	Daniele Rossi, André K. Nieuwland, Cecilia Metra	Simultaneous Switching Noise: The Relation between Bus Layout and Coding.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques
1	Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong	Fast Dummy-Fill Density Analysis With Coupling Constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Charbel J. Akl, Magdy A. Bayoumi	Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Karthik Baddam, Mark Zwolinski	Divided Backend Duplication Methodology for Balanced Dual Rail Routing.	CHES	2008	DBLP DOI BibTeX RDF	Dual Rail Routing, Dual Rail FPGA Implementation, Differential Power Analysis
1	Roberto Gómez, Alejandro Girón, Víctor H. Champac	A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Interconnection opens, Boolean testing, Favorable logic conditions, Test generation methodology, Coupling capacitances
1	Kunal P. Ganeshpure, Sandip Kundu	Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.	DATE	2007	DBLP DOI BibTeX RDF
1	Prashant Agrawal, R. Srinivasa, Ajit N. Oke, Saurabh Vijay	A path based modeling approach for dynamic power estimation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	thermal design power, power modeling
1	Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham	Estimating path delay distribution considering coupling noise.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	dynamic delay variation, coupling, crosstalk
1	Hanif Fatemi, Behnam Amelifard, Massoud Pedram	Power optimal MTCMOS repeater insertion for global buses.	ISLPED	2007	DBLP DOI BibTeX RDF	MTCMOS circuits, low-power design, buffer insertion
1	Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy	A robust edge encoding technique for energy-efficient multi-cycle interconnect.	ISLPED	2007	DBLP DOI BibTeX RDF	multi-cycle interconnect, interconnect, encoding, repeaters
1	Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong	Dummy fill density analysis with coupling constraints.	ISPD	2007	DBLP DOI BibTeX RDF	CMP, coupling, dummy fills
1	Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu	Exploiting on-chip data behavior for delay minimization.	SLIP	2007	DBLP DOI BibTeX RDF	coding, crosstalk, deep-submicron
1	Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang	Coupling-aware Dummy Metal Insertion for Lithography.	ASP-DAC	2007	DBLP DOI BibTeX RDF	coupling-aware dummy metal insertion, integrated circuits manufacturing technology, resolution enhancement techniques, off-axis illumination, forbidden pitches, printability improvement, invisible dummy metal segments, lithography cost minimization, optimal algorithm, chemical mechanical polish
1	Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue	Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Youngmin Kim, Dusan Petranovic, Dennis Sylvester	Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion.	ASP-DAC	2007	DBLP DOI BibTeX RDF	capacitance increment, metal fill insertion, inter level dielectric thickness planarity, metal dummy, signal capacitance, electrical characteristic, signal dimensions, dummy shape, dummy dimensions, simple test patterns, benchmark circuits, weighting function
1	Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay	An Approach for Pre-Silicon Power Modeling.	ICCTA	2007	DBLP DOI BibTeX RDF
1	Syed Rafay Hasan, Yvon Savaria	Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Charbel J. Akl, Magdy A. Bayoumi	Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion.	ISQED	2007	DBLP DOI BibTeX RDF
1	Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay	A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Sujan Pandey, Christian Genz, Rolf Drechsler	Co-synthesis of custom on-chip bus and memory for MPSoC architectures.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou	Handling Pattern-Dependent Delay Faults in Diagnosis.	VTS	2007	DBLP DOI BibTeX RDF
1	Mini Nanua, David Blaauw	Crosstalk Waveform Modeling Using Wave Fitting.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue	Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn	Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen	Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs.	ISPD	2006	DBLP DOI BibTeX RDF	fault-tolerant, reliability, low power, coupling capacitance
1	Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru Qiu	Low-power bus encoding using an adaptive hybrid algorithm.	DAC	2006	DBLP DOI BibTeX RDF	data probabilistic distribution, delayed bus, weighted code mapping, window based change detection, low power, adaptive algorithm, bus encoding
1	Leonard Lee, Li-C. Wang	On bounding the delay of a critical path.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang	Crosstalk minimization in logic synthesis for PLAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	synthesis, Crosstalk, PLA, domino logic
1	Jo C. Ebergen, Alex Chow, Bill Coates, Justin Schauer, David Hopkins	An Asynchronous High-Throughput Control Circuit For Proximity Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu	Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm.	DSD	2006	DBLP DOI BibTeX RDF	crosstalk avoidance codes, interconnect energy, networks on chip, crosstalk, wormhole switching
1	Avnish R. Brahmbhatt, Jingyi Zhang, Qinru Qiu, Qing Wu	Adaptive low-power bus encoding based on weighted code mapping.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri	Memory-based crosstalk canceling CODECs for on-chip buses.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Henning Gundersen, Yngvar Berg	A novel ternary more, less and equality circuit using recharged semi-floating gate devices.	ISCAS	2006	DBLP DOI BibTeX RDF
1	K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas	A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao	Coupling aware RLC-based clock routings for crosstalk minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Henning Gundersen, Yngvar Berg	A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Kambiz Samadi, Puneet Sharma	Study of Floating Fill Impact on Interconnect Capacitance.	ISQED	2006	DBLP DOI BibTeX RDF
1	Amitava Bhaduri, Ranga Vemuri	Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis	Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne	Logical effort model extension to propagation delay representation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Lin Xie, Peiliang Qiu, Qinru Qiu	Partitioned bus coding for energy reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Amitava Bhaduri, Ranga Vemuri	Moment-driven coupling-aware routing methodology.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	coupling-aware, routing, moments
1	Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa	Interconnect capacitance extraction for system LCD circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	interconnect capacitance, system LCD, capacitance extraction
1	Liang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
1	Di Wu, Jiang Hu, Rabi N. Mahapatra	Coupling aware timing optimization and antenna avoidance in layer assignment.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect
1	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity
1	Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
1	Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Kishore Kumar Muchherla, Pinhong Chen, Janet Meiling Wang	A non-iterative equivalent waveform model for timing analysis in presence of crosstalk.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Medha Kulkarni, Tom Chen	A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Lin Zhong, Niraj K. Jha	Interconnect-aware low-power high-level synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Siu-Kei Wong, Chi-Ying Tsui	Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus.	DATE	2004	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, interconnects, buses, coupling capacitance
1	Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu	A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Haoxing Ren, David Zhigang Pan, Paul Villarrubia	True crosstalk aware incremental placement with noise map.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Chunjie Duan, Sunil P. Khatri	Exploiting Crosstalk to Speed up On-Chip Buse.	DATE	2004	DBLP DOI BibTeX RDF
1	Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang	Crosstalk Minimization in Logic Synthesis for PLA.	DATE	2004	DBLP DOI BibTeX RDF
1	José Luis Rosselló, Jaume Segura	A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk.	DATE	2004	DBLP DOI BibTeX RDF
1	Davide Pandini, Cristiano Forzan, Livio Baldi	Design Methodologies and Architecture Solutions for High-Performance Interconnects.	ICCD	2004	DBLP DOI BibTeX RDF
1	Medha Kulkarni, Tom Chen	A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects.	ISQED	2004	DBLP DOI BibTeX RDF
1	Fangqing Yu, Weiping Shi	A Divide-and-Conquer Algorithm for 3D Capacitance Extraction.	ISQED	2004	DBLP DOI BibTeX RDF
1	Madhu Mutyam	Preventing Crosstalk Delay using Fibonacci Representation.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Weiping Shi, Fangqing Yu	A divide-and-conquer algorithm for 3-D capacitance extraction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne	Physical Extension of the Logical Effort Model.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu	On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Yu Chen, Puneet Gupta, Andrew B. Kahng	Performance-impact limited area fill synthesis.	DAC	2003	DBLP DOI BibTeX RDF	VLSI manufacturability, coupling capacitance extraction, dummy fill problem, signal delay, linear programming, greedy method
1	Li-Da Huang, Hung-Ming Chen, D. F. Wong	Global Wire Bus Configuration with Minimum Delay Uncertainty.	DATE	2003	DBLP DOI BibTeX RDF
1	Ryon M. Smey, Bill Swartz, Patrick H. Madden	Crosstalk Reduction in Area Routing.	DATE	2003	DBLP DOI BibTeX RDF
1	L. Di Silvio, Daniele Rossi, Cecilia Metra	Crosstalk Effect Minimization for Encoded Busses.	IOLTS	2003	DBLP DOI BibTeX RDF
1	Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong	Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis.	ISQED	2003	DBLP DOI BibTeX RDF
1	Shabbir H. Batterywala, Narendra V. Shenoy	A Method to Estimate Slew and Delay in Coupled Digital Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Li Ding 0002, David T. Blaauw, Pinaki Mazumder	Accurate crosstalk noise modeling for early signal integrity analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	David Blaauw, Supamas Sirichotiyakul, Chanhee Oh	Driver modeling and alignment for worst-case delay noise.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	R. Hossain, F. Viglione, M. Cavalli	Designing fast on-chip interconnects for deep submicrometer technologies.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Jiang Xu, Wayne Wolf	Wave pipelining for application-specific networks-on-chips.	CASES	2002	DBLP DOI BibTeX RDF	system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance
1	Lin Zhong, Niraj K. Jha	Interconnect-aware high-level synthesis for low power.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh	Noise Injection and Propagation in High Performance Designs. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF