Search results for "cpu architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Xin Cai, Martin A. Brooke	A compact CPU architecture for sensor signal processing.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Iván Contreras, Yiyi Jiang, José Ignacio Hidalgo, Laura Núñez-Letamendia	Using a GPU-CPU architecture to speed up a GA-based real-time system for trading the stock market.	Soft Comput.	2012	DBLP DOI BibTeX RDF
1	Victor W. Lee, Changkyu Kim, Jatin Chhugani, Michael Deisher, Daehyun Kim, Anthony D. Nguyen, Nadathur Satish, Mikhail Smelyanskiy, Srinivas Chennupaty, Per Hammarlund, Ronak Singhal, Pradeep Dubey	Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU.	ISCA	2010	DBLP DOI BibTeX RDF	cpu architecture, gpu architecture, throughput computing, performance analysis, performance measurement, software optimization
1	John A. Tsakok	Faster incoherent rays: Multi-BVH ray stream tracing.	High Performance Graphics	2009	DBLP DOI BibTeX RDF	MBVH, MBVH RS, QBVH, incoherent rays, ray traversal, real time, ray tracing, global illumination, path tracing
1	Carsten Trinitis, Michael Bader, Martin Schulz	8th International Special Session on Current Trends in Numerical Simulation for Parallel Engineering Environments.	PVM/MPI	2009	DBLP DOI BibTeX RDF
1	Christian Schäck, Wolfgang Heenes, Rolf Hoffmann	A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA.	SAMOS	2009	DBLP DOI BibTeX RDF	Global Cellular Automata, FPGA, multiprocessor architecture, omega network
1	Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, William Macy, Mostafa Hagog, Yen-Kuang Chen, Akram Baransi, Sanjeev Kumar, Pradeep Dubey	Efficient implementation of sorting on multi-core SIMD CPU architecture.	PVLDB	2008	DBLP BibTeX RDF
1	Jack Whitham, Neil C. Audsley	Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF	wcet, reduction, trace, hard real-time, scratchpads
1	Priya Govindarajan, Srihari Makineni, Donald Newell, Ravi R. Iyer, Ram Huggahalli, Amit Kumar	Achieving 10Gbps Network Processing: Are We There Yet?.	HiPC	2008	DBLP DOI BibTeX RDF	Large Receive Offload, LRO, Direct Cache Access, TOE, TCP/IP acceleration, de-fragmentation, receive offload, receive side coalescing, RSC, DCA
1	Carsten Trinitis, Martin Schulz	7th International Special Session on Current Trends in Numerical Simulation for Parallel Engineering Environments: New Directions and Work-in-Progress (ParSim 2008).	PVM/MPI	2008	DBLP DOI BibTeX RDF
1	Allison L. Holloway, Vijayshankar Raman, Garret Swart, David J. DeWitt	How to barter bits for chronons: compression and bandwidth trade offs for database scans.	SIGMOD Conference	2007	DBLP DOI BibTeX RDF	bandwidth trade offs, difference coding, compression, Huffman coding
1	David Montgomery, Ali Akoglu	Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications.	ASAP	2007	DBLP DOI BibTeX RDF
1	Carsten Trinitis, Martin Schulz	6th International Special Session on Current Trends in Numerical Simulation for Parallel Engineering Environments New Directions and Work-in-Progress ParSim 2007.	PVM/MPI	2007	DBLP DOI BibTeX RDF
1	Yosi Ben-Asher, Danny Meisler	Towards a Source Level Compiler: Source Level Modulo Scheduling.	ICPP Workshops	2006	DBLP DOI BibTeX RDF
1	Jack Whitham, Neil C. Audsley	MCGREP - A Predictable Architecture for Embedded Real-Time Systems.	RTSS	2006	DBLP DOI BibTeX RDF
1	Yosi Ben-Asher, Danny Meisler	Towards a Source Level Compiler: Source Level Modulo Scheduling.	Program Analysis and Compilation	2006	DBLP DOI BibTeX RDF
1	Peter J. Vidler, Michael J. Pont	Computer Assisted Source-Code Parallelisation.	ICCSA	2006	DBLP DOI BibTeX RDF
1	Carsten Trinitis, Martin Schulz	5th International Special Session on Current Trends in Numerical Simulation for Parallel Engineering Environments.	PVM/MPI	2006	DBLP DOI BibTeX RDF
1	Arvind Seshadri, Mark Luk, Elaine Shi, Adrian Perrig, Leendert van Doorn, Pradeep K. Khosla	Pioneer: verifying code integrity and enforcing untampered code execution on legacy systems.	SOSP	2005	DBLP DOI BibTeX RDF	dynamic root of trust, self-check-summing code, software-based code attestation, verifiable code execution, rootkit detection
1	Bharat B. Madan, Shashi Phoha, Kishor S. Trivedi	StackOFFence: A Technique for Defending Against Buffer Overflow Attacks.	ITCC	2005	DBLP DOI BibTeX RDF
1	Xizhi Li, Tiecai Li	ECOMIPS: An Economic MIPS CPU Design on FPGA.	IWSOC	2004	DBLP DOI BibTeX RDF
1	Radim Ballner, Pavel Tvrdík	MOOSS: CPU Architecture with Memory Protection and Support for OOP.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
1	Brandon Eames, Ted Bapty, Ben Abbott, Sandeep Neema, Kumar Chhokra	Model-Integrated Design Toolset for Polymorphous Computer-Based Systems.	ECBS	2003	DBLP DOI BibTeX RDF
1	Nick Richardson, Lun Bin Huang, Razak Hossain, Julian Lewis, Tommy Zounes, Naresh Soni	The iCore 520-MHz Synthesizable CPU Core.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh Soni, Julian Lewis	The iCOREtm 520 MHz synthesizable CPU core.	DAC	2002	DBLP DOI BibTeX RDF	high-frequency, st20, cache, synthesis, pipeline, embedded, ASIC, branch-prediction, microarchitecture, CPU
1	Vinodh Cuppu, Bruce L. Jacob	Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?.	ISCA	2001	DBLP DOI BibTeX RDF	Systems Application Architecture
1	Takashi Egawa, Koji Hino, Yohei Hasegawa	Fast and Secure Packet Processing Environment for Per-Packet QoS Customization.	IWAN	2001	DBLP DOI BibTeX RDF
1	Jeff Scott, Lea Hwang Lee, Ann Chin, John Arends, Bill Moyer	Designing the M·CORETM M3 CPU Architecture.	ICCD	1999	DBLP DOI BibTeX RDF	embedded processor core, Low-power, high-performance, embedded applications
1	Haruna R. Isa, William R. Shockley, Cynthia E. Irvine	A Multi-Threading Architecture for Multilevel Secure Transaction Processing. (PDF / PS)	IEEE Symposium on Security and Privacy	1999	DBLP DOI BibTeX RDF
1	C.-K. V. Tien, K. Lewis, Hans J. Greub, T. Tsen, John F. McDonald	Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
1	Luddy Harrison	Examination of a Memory Access Classification Scheme for Pointer-Intensive and Numeric Programs.	International Conference on Supercomputing	1996	DBLP DOI BibTeX RDF	CPU architecture, instruction profiling, memory access pattern classification, memory latency tolerance, data cache
1	Michael Gschwind	Reprogrammable hardware for educational purposes.	SIGCSE	1994	DBLP DOI BibTeX RDF
1	Yap Siong Chua, Charles N. Winton	A Simulation Tool for Teaching CPU Design and Microprogramming Concepts.	APL	1989	DBLP DOI BibTeX RDF	APL
1	David S. Lindsay, Thomas E. Bell	Directed Benchmarks for CPU Architecture Evaluation.	Int. CMG Conference	1986	DBLP BibTeX RDF