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Results
Found 4 publication records. Showing 4 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia |
Fast discrete function evaluation using decision diagrams.  |
ICCAD  |
1995 |
DBLP DOI BibTeX RDF |
address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams |
| 1 | Alper Sen, Baris Aksanli, Murat Bozkurt |
Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units.  |
International Journal of Parallel Programming  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Alper Sen, Baris Aksanli, Murat Bozkurt, Melih Mert |
Parallel Cycle Based Logic Simulation Using Graphics Processing Units.  |
ISPDC  |
2010 |
DBLP DOI BibTeX RDF |
verification, GPU, CUDA, design automation |
| 1 | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
A fast logic simulator using a look up table cascade emulator.  |
ASP-DAC  |
2006 |
DBLP DOI BibTeX RDF |
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