Search results for "data cache"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Soontae Kim, Jongmin Lee 0002	Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, data cache, write buffer
3	Vinayak Puranik, Tulika Mitra, Y. N. Srikant	Probabilistic modeling of data cache behavior.	EMSOFT	2009	DBLP DOI BibTeX RDF	data cache modeling, probabilistic execution time analysis
3	Jongmin Lee 0002, Soontae Kim	An energy-delay efficient 2-level data cache architecture for embedded system.	ISLPED	2009	DBLP DOI BibTeX RDF	2-level data cache, early cache hit predictor, one-way write
3	Xavier Vera, Björn Lisper, Jingling Xue	Data cache locking for tight timing calculations.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	data cache analysis, embedded systems, Worst-case execution time, safety critical systems
3	Jean Christophe Beyler, Philippe Clauss	Performance driven data cache prefetching in a dynamic software optimization system.	ICS	2007	DBLP DOI BibTeX RDF	binary instrumentation, data cache prefetching, dynamic optimization
3	Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Soft error and energy consumption interactions: a data cache perspective.	ISLPED	2004	DBLP DOI BibTeX RDF	energy-efficiency, soft error, data cache
3	Xavier Vera, Björn Lisper, Jingling Xue	Data cache locking for higher program predictability.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	data cache analysis, worst-case execution time
3	Andreas Moshovos, Gurindar S. Sohi	Streamlining Inter-Operation Memory Communication via Data Dependence Prediction.	MICRO	1997	DBLP BibTeX RDF	DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation
3	Chun Xia, Josep Torrellas	Improving the Data Cache Performance of Multiprocessor Operating Systems.	HPCA	1996	DBLP DOI BibTeX RDF	data cache performance, operating system effect on caches, bus-based multiprocessor, address trace evaluation, block operations, latency hiding
3	Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau	Reducing memory latency using a small software driven array cache.	HICSS	1995	DBLP DOI BibTeX RDF	small software driven array cache, data references, array reference, nonarray reference, data cache designs, cache space, cache control mechanisms, array references, data cache performance, hardware driven data prefetching scheme, software driven cache design, array cache, low runtime overhead, performance evaluation, data structures, compiler, programming, programming, prefetching, program compilers, cache storage, cache performance, temporal locality, spatial locality, memory latency
2	Jun Wang, Xiaoyu Yao, Christopher Mitchell, Peng Gu	A New Hierarchical Data Cache Architecture for iSCSI Storage Server.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
2		Data Cache.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
2	Yu Liu, Wei Zhang 0002	Exploiting stack distance to estimate worst-case data cache performance.	SAC	2009	DBLP DOI BibTeX RDF	stack distance, cache, timing analysis, worst-case execution time
2	Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado	Stack oriented data cache filtering.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	power-performance efficient design, memory hierarchy, cache memory
2	Wolfgang Puffitsch	Data caching, garbage collection, and the Java memory model.	JTRES	2009	DBLP DOI BibTeX RDF	Java memory model, garbage collection, data cache
2	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks	Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.	IEEE Micro	2008	DBLP DOI BibTeX RDF	caches, process variation, variability, dynamic memory
2	Subhradyuti Sarkar, Dean M. Tullsen	Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture.	HiPEAC	2008	DBLP DOI BibTeX RDF
2	Garo Bournoutian, Alex Orailoglu	Miss reduction in embedded processors through dynamic, power-friendly cache design.	DAC	2008	DBLP DOI BibTeX RDF	dynamic associativity, multi-core, embedded processors, data cache
2	Harini Ramaprasad, Frank Mueller	Bounding Worst-Case Response Time for Tasks with Non-Preemptive Regions.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF	real-time, timing analysis, data cache
2	Ismail Kadayif, Mahmut T. Kandemir	Modeling and improving data cache reliability.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	vulnerability factors, reliability, data integrity, soft errors, data caches
2	Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin	MPSoC memory optimization using program transformation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, data cache, Data locality, compiler transformations
2	Yefim Shuf, Ian M. Steiner	Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations.	ISPASS	2007	DBLP DOI BibTeX RDF	J2EE workload, Java benchmarks, SPECjvm98, SPECjbb2000, Java 2 Enterprise Edition, SPECjAppServer2004, systems research, software research, cache-to-cache modified data transfers, intelligent thread co-scheduling, Java heap, bursty data cache, Java virtual method calls, optimizations, performance analysis, garbage collection, instruction cache, data prefetching, commercial workload
2	Vilas Sridharan, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli	Reducing Data Cache Susceptibility to Soft Errors.	IEEE Trans. Dependable Sec. Comput.	2006	DBLP DOI BibTeX RDF	refresh, refetch, Fault tolerance, reliability, cache memories, soft errors, error modeling
2	Shuai Wang, Jie S. Hu, Sotirios G. Ziavras	On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
2	Pengyong Ma, Xiao Hu, Shuming Chen, Yang Guo	Pseudo Share Data Cache in Multiprocessor: PSDMP.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
2	Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim	Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	embedded system, low-power, multimedia application, cache architecture
2	Javed Absar, Francky Catthoor	Analysis of scratch-pad and data-cache performance using statistical methods.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Jan Staschulat, Rolf Ernst	Worst case timing analysis of input dependent data cache behavior.	ECRTS	2006	DBLP DOI BibTeX RDF
2	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	A Reconfigurable Data Cache for Adaptive Processors.	ARC	2006	DBLP DOI BibTeX RDF
2	Harini Ramaprasad, Frank Mueller	Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
2	Wei Zhang 0002, Mahmut T. Kandemir, Mustafa Karaköy, Guangyu Chen	Reducing data cache leakage energy using a compiler-based approach.	ACM Trans. Embedded Comput. Syst.	2005	DBLP DOI BibTeX RDF	array-intensive applications, pointer-intensive applications, data caches, energy optimization, Compiler analysis
2	Kyle J. Nesbit, James E. Smith	Data Cache Prefetching Using a Global History Buffer.	IEEE Micro	2005	DBLP DOI BibTeX RDF
2	Wei Zhang	Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	write-back cache, in-cache replication, Soft error
2	Enric Gibert, F. Jesús Sánchez, Antonio González	Distributed Data Cache Designs for Clustered VLIW Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	design styles, Single data stream architectures
2	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Performance and Power Evaluation of an Intelligently Adaptive Data Cache.	HiPC	2005	DBLP DOI BibTeX RDF
2	Pradeep Nalabalapu, Ron Sass	Bandwidth Management with a Reconfigurable Data Cache.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Mehdi Modarressi, Maziar Goudarzi, Shaahin Hessabi	Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
2	Xiaoyu Yao, Jun Wang	Toward Effective NIC Caching: A Hierarchical Data Cache Architecture for iSCSI Storage Servers.	ICPP	2005	DBLP DOI BibTeX RDF
2	José R. Brunheroto, Valentina Salapura, Fernando F. Redigolo, Dirk Hoenicke, Alan Gara	Data cache prefetching design space exploration for BlueGene/L supercomputer.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
2	Harini Ramaprasad, Frank Mueller	Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
2	Jan-Willem van de Waerdt, Stamatis Vassiliadis, Jean-Paul van Itegem, Hans Van Antwerpen	The TM3270 Media-Processor Data Cache.	ICCD	2005	DBLP DOI BibTeX RDF
2	Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke	Automated data cache placement for embedded VLIW ASIPs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	cache, ASIP, cache optimization, embedded applications
2	Jingling Xue, Xavier Vera	Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	performance evaluation, analytical modeling, cache memories, data locality, Modeling techniques
2	Peng-fei Chuang, Resit Sendag, David J. Lilja	Improving Data Cache Performance via Address Correlation: An Upper Bound Study.	Euro-Par	2004	DBLP DOI BibTeX RDF
2	Wei Zhang 0002	Compiler-Directed Data Cache Leakage Reduction.	ISVLSI	2004	DBLP DOI BibTeX RDF
2	Wei Zhang	Enhancing data cache reliability by the addition of a small fully-associative replication cache.	ICS	2004	DBLP DOI BibTeX RDF	in-cache replication, write-back cache, soft error
2	Kyle J. Nesbit, James E. Smith	Data Cache Prefetching Using a Global History Buffer.	HPCA	2004	DBLP DOI BibTeX RDF
2	G. Surendra, Subhasis Banerjee, S. K. Nandy	On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort.	WMPI	2004	DBLP DOI BibTeX RDF	cache traffic, intrusion detection, pattern matching, network processor, instruction reuse
2	Enric Gibert, F. Jesús Sánchez, Antonio González	Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.	CGO	2003	DBLP DOI BibTeX RDF
2	Jun Yang 0002, Youtao Zhang	Lightweight set buffer: low power data cache for multimedia application.	ISLPED	2003	DBLP DOI BibTeX RDF	multimedia, low power, cache
2	Carlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella	Non redundant data cache.	ISLPED	2003	DBLP DOI BibTeX RDF	value replication, low power, compression, cache memories
2	Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram	Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power TLB, multi-ported memory structures, energy optimization, low-power cache
2	Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau	Reducing data cache energy consumption via cached load/store queue.	ISLPED	2003	DBLP DOI BibTeX RDF	LSQ, load queue, store queue, low power, cache, memory, low energy, low latency
2	Khalil Amiri, Sanghyun Park, Renu Tewari, Sriram Padmanabhan	DBProxy: A dynamic data cache for Web applications.	ICDE	2003	DBLP DOI BibTeX RDF
2	Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen	The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System.	MICRO	2003	DBLP DOI BibTeX RDF	Linux, Intel
2	Wei Zhang 0002, Mustafa Karaköy, Mahmut T. Kandemir, Guangyu Chen	A compiler approach for reducing data cache energy.	ICS	2003	DBLP DOI BibTeX RDF	data caches, energy optimization, compiler analysis
2	Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum	A Data Cache with Dynamic Mapping.	LCPC	2003	DBLP DOI BibTeX RDF
2	Jaume Abella, Antonio González	Power Efficient Data Cache Designs.	ICCD	2003	DBLP DOI BibTeX RDF
2	Martin Burtscher, Amer Diwan, Matthias Hauswirth	Static Load Classification for Improving the Value Predictability of Data-Cache Misses.	PLDI	2002	DBLP DOI BibTeX RDF	load-value prediction, type-based analysis
2	Khalil Amiri, Sanghyun Park, Renu Tewari	A self-managing data cache for edge-of-network web applications.	CIKM	2002	DBLP DOI BibTeX RDF	e-commerce, dynamic content, semantic caching
2	Terry Lyon, Eric Delano, Cameron McNairy, Dean Mulla	Data Cache Design Considerations for the Itanium® 2 Processor.	ICCD	2002	DBLP DOI BibTeX RDF
2	Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai	Bloom filtering cache misses for accurate data speculation and prefetching.	ICS	2002	DBLP DOI BibTeX RDF	bloom filter, instruction scheduling, data cache, data prefetching, data speculation
2	Jun Yang 0002, Rajiv Gupta	Frequent value locality and its applications.	ACM Trans. Embedded Comput. Syst.	2002	DBLP DOI BibTeX RDF	Frequently occurring values, encoding techniques, low power data bus, low power data cache, value profiling
2	Manuel E. Acacio, José González, José M. García, José Duato	A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	L2 misses, On-chip Integration, Three-Level Directory, Shared Data Cache, Scalability, cc-NUMA
2	Donglok Kim, Ravi Managuli, Yongmin Kim	Data Cache and Direct Memory Access in Programming Mediaprocessors.	IEEE Micro	2001	DBLP DOI BibTeX RDF
2	G. Hariprakash, R. Achutharaman, Amos Omondi	DSTRIDE: Data-Cache Miss-Address-Based Stride Prefetching Scheme for Multimedia Processors.	ACSAC	2001	DBLP DOI BibTeX RDF
2	Peter Petrov, Alex Orailoglu	Towards effective embedded processors in codesigns: customizable partitioned caches.	CODES	2001	DBLP DOI BibTeX RDF	reprogrammable customizations, embedded processors, data cache
2	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee	A High-Bandwidth Memory Pipeline for Wide Issue Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Data bandwidth, runtime stack, data stream partitioning, multiported data cache, instruction level parallelism, data locality
2	Julio Sahuquillo, Ana Pont, Veljko M. Milutinovic	The Filter Data Cache: A Tour Management Comparison with Related Split Data Cache Schemes Sensitive to Data Localities.	ISHPC	2000	DBLP DOI BibTeX RDF
2	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	system design, data cache, data partitioning, system synthesis, scratch-pad memory, on-chip memory, memory synthesis
2	Julio Sahuquillo, Ana Pont	Designing Competitive Coherence Protocols Taking Advantage of Reuse Information.	EUROMICRO	2000	DBLP DOI BibTeX RDF	split data cache, reuse information, competitive protocol, performance evaluation, multiprocessor systems, data locality
2	Chi-Hung Chi, Jun-Li Yuan	Design Considerations of High Performance Data Cache with Prefetching.	Euro-Par	1999	DBLP DOI BibTeX RDF
2	Brian R. Fisk, R. Iris Bahar	The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency.	ICCD	1999	DBLP DOI BibTeX RDF	Algorithms, Architecture, Caches
2	Teresa L. Johnson, Daniel A. Connors, Matthew C. Merten, Wen-mei W. Hwu	Run-Time Cache Bypassing.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	cache bypassing, Data cache, cache management, temporal locality, spatial locality
2	Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau	Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	data cache, Loop tiling, data alignment, cache conflict
2	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Data Cache Sizing for Embedded Processor Applications.	DATE	1998	DBLP DOI BibTeX RDF
2	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Memory data organization for improved cache performance in embedded processor applications.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	system design, cache memory, data cache, system synthesis, memory synthesis
2	F. Jesús Sánchez, Antonio González, Mateo Valero	Static Locality Analysis for Cache Management.	IEEE PACT	1997	DBLP DOI BibTeX RDF	Selective Cache, Dual Data Cache, Locality analysis
2	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Memory Organization for Improved Data Cache Performance in Embedded Processors. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF
2	Yue Liu, David R. Kaeli	Branch-Directed and Stride-Based Data Cache Prefetching. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF
2	Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi	Streamlining Data Cache Access with Fast Address Calculation.	ISCA	1995	DBLP DOI BibTeX RDF
2	Chi-Hung Chi, Siu-Chung Lau	Reducing data access penalty using intelligent opcode-driven cache prefetching. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	data access penalty, intelligent opcode-driven, LOAD-UPDATE, LOAD-MODIFY, IBM PowerPC, HP Precision Architecture, intelligent data prefetching, instruction decode unit, storage management, data cache, cache storage, cache prefetching
2	David Callahan, Allan Porterfield	Data cache performance of supercomputer applications.	SC	1990	DBLP BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Circuit design of a dual-versioning L1 data cache.	Integration	2012	DBLP DOI BibTeX RDF
1	Juan Segarra, Clemente Rodríguez, Ruben Gran Tejero, Luis C. Aparicio, Victor Viñals	A Small and Effective Data Cache for Real-Time Multitasking Systems.	IEEE Real-Time and Embedded Technology and Applications Symposium	2012	DBLP DOI BibTeX RDF
1	Sangyeol Kang, Alexander G. Dean	Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation.	IEEE Real-Time and Embedded Technology and Applications Symposium	2012	DBLP DOI BibTeX RDF
1	Ganesh Balakrishnan, Yan Solihin	WEST: Cloning data cache behavior using Stochastic Traces.	HPCA	2012	DBLP DOI BibTeX RDF
1	Jiongyao Ye, Yu Wan, Takahiro Watanabe	An Adaptive Various-Width Data Cache for Low Power Design.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Minhaj Ahmad Khan	Data Cache Prefetching With Dynamic Adaptation.	Comput. J.	2011	DBLP DOI BibTeX RDF
1	Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero	Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.	PACT	2011	DBLP DOI BibTeX RDF
1	Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Circuit design of a dual-versioning L1 data cache for optimistic concurrency.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Hector Posadas, Luis Diaz, Eugenio Villar	Fast data-cache modeling for native co-simulation.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Mohsen Taherian, Amirali Baniasadi, Hamid Noori	Instruction and data cache peak temperature reduction using cache access balancing in embedded processors.	AICCSA	2011	DBLP DOI BibTeX RDF
1	Bach Khoa Huynh, Lei Ju, Abhik Roychoudhury	Scope-Aware Data Cache Analysis for WCET Estimation.	IEEE Real-Time and Embedded Technology and Applications Symposium	2011	DBLP DOI BibTeX RDF
1	Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado	Stack filter: Reducing L1 data cache power consumption.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	P. Carazo, R. Apolloni, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado	L1 Data Cache Power Reduction Using a Forwarding Predictor.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Dan R. K. Ports, Austin T. Clements, Irene Zhang, Samuel Madden, Barbara Liskov	Transactional Consistency and Automatic Management in an Application Data Cache.	OSDI	2010	DBLP BibTeX RDF
1	Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles Canada	A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	An Efficient Non-blocking Data Cache for Soft Processors.	ReConFig	2010	DBLP DOI BibTeX RDF