Search results for "dataflow graph"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Nathan Clark, Hongtao Zhong, Wilkin Tang, Scott A. Mahlke	Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration.	International Journal of Parallel Programming	2003	DBLP DOI BibTeX RDF	hardware customization, embedded system, instruction set, application-specific processor, dataflow graph
2	Suriya Subramanian, Kathryn S. McKinley	HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.	HiPEAC	2009	DBLP DOI BibTeX RDF
2	Hyunuk Jung, Hoeseok Yang, Soonhoi Ha	Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	VHDL, system level design, RTL, dataflow graph (DFG), HW/SW codesign
2	Tsung-Hsi Chiang, Lan-Rong Dung	System-level verification on high-level synthesis of dataflow graph.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Hyunuk Jung, Soonhoi Ha	Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	automatic hardware synthesis, VHDL, system level design, dataflow graph(DFG), HW/SW codesign
2	Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu	Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors.	ISPAN	1996	DBLP DOI BibTeX RDF	edge-weighted directed acyclic graph, bounded number of processors scheduling, arbitrary processor network, scheduling, scheduling, parallel programming, processor scheduling, data flow graphs, task graphs, parallel processors, dataflow graph
2	S. T. Kim, K. Suwunboriruksa, S. Herath, Anura P. Jayasumana, Jayantha A. Herath	Algorithmic Transformations for Neural Computing and Performance of Supervised Learning on a Dataflow Machine.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	reprogrammable dataflow neural classifiers, neural-dataflow transformations, dataflow algorithmic transformations, dataflow multiprocessors, high level data dependency, machine executable low-level dataflow graph, tagged token dataflow algorithmic transformation, performance evaluation, performance, parallel architectures, supervised learning, neural nets, granularity, learning systems, functional languages, neural computing, computerized pattern recognition, algorithmic transformations, dataflow machine
2	Edward A. Lee	Consistency in Dataflow Graphs.	IEEE Trans. Parallel Distrib. Syst.	1991	DBLP DOI BibTeX RDF	synchronous dataflow graphs, dataflow graphsemantics, token-flow model, graphtheory, programming languages, deadlock, programming theory, consistency checks, dataflow graphs, dataflow graph
1	Jorge Luiz e Silva, Joelmir Jose Lopes, Bruno de Abreu Silva, Antonio Carlos Fernandes da Silva	Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System	CoRR	2011	DBLP BibTeX RDF
1	Tae-ho Shin, Hyunok Oh, Soonhoi Ha	Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan	Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.	ARC	2011	DBLP DOI BibTeX RDF
1	Haitao Wei, Junqing Yu, Huafei Yu, Guang R. Gao	Minimizing communication in rate-optimal software pipelining for stream programs.	CGO	2010	DBLP DOI BibTeX RDF	dfbrook, multi-core, software pipelining, cell processor, stream programs
1	Craig Chambers, Ashish Raniwala, Frances Perry, Stephen Adams, Robert R. Henry, Robert Bradshaw, Nathan Weizenbaum	FlumeJava: easy, efficient data-parallel pipelines.	PLDI	2010	DBLP DOI BibTeX RDF	java, mapreduce, data-parallel programming
1	Akira Kuroda, Mayuko Koezuka, Hidenori Matsuzaki, Takashi Yoshikawa, Shigehiro Asano	Mapping method for dynamically reconfigurable architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	William Plishker, Nimish Sane, Shuvra S. Bhattacharyya	Mode grouping for more effective generalized scheduling of dynamic dataflow applications.	DAC	2009	DBLP DOI BibTeX RDF	mode grouping, scheduling, dataflow
1	Samir Jafar, Axel W. Krings, Thierry Gautier	Flexible Rollback Recovery in Dynamic Heterogeneous Grid Computing.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
1	Rim Chayeh, Christophe Cérin, Mohamed Jemni	A Probabilistic Fault-Tolerant Recovery Mechanism for Task and Result Certification of Large-Scale Distributed Applications.	GPC	2009	DBLP DOI BibTeX RDF	Probabilistic certification, Fault-Tolerance by value, Distributed systems, Recovery, Result checking, Meta-computing
1	Qiming Chen, Meichun Hsu	Cooperating SQL Dataflow Processes for In-DB Analytics.	OTM Conferences	2009	DBLP DOI BibTeX RDF
1	Katherine E. Coons, Behnam Robatmili, Matthew E. Taylor, Bertrand A. Maher, Doug Burger, Kathryn S. McKinley	Feature selection and policy optimization for distributed instruction placement using reinforcement learning.	PACT	2008	DBLP DOI BibTeX RDF	compiler heuristics, genetic algorithms, neural networks, machine learning, instruction scheduling
1	Hyunchul Park, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-seok Kim	Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.	PACT	2008	DBLP DOI BibTeX RDF	operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture
1	Michael J. Flynn, Robert G. Dimond, Oskar Mencer, Oliver Pell	Finding Speedup in Parallel Processors.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley	Strategies for mapping dataflow blocks to distributed hardware.	MICRO	2008	DBLP DOI BibTeX RDF
1	Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij	Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip.	NOCS	2008	DBLP DOI BibTeX RDF	Cyclo-Static Dataflow, System on Chip, Network on Chip, Real-Time Performance
1	Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous	The Significance of Affectors and Affectees Correlations for Branch Prediction.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya	Memory-constrained Block Processing for DSP Software Optimization.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	block processing, block diagram compiler, activation overhead, embedded systems, memory management, vectorization, dataflow, context switch
1	Michael Isard, Mihai Budiu, Yuan Yu, Andrew Birrell, Dennis Fetterly	Dryad: distributed data-parallel programs from sequential building blocks.	EuroSys	2007	DBLP DOI BibTeX RDF	concurrency, cluster computing, distributed programming, dataflow
1	Girish Venkataramani, Seth Copen Goldstein	Operation chaining asynchronous pipelined circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya	Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	block diagram compiler, hierarchical graph decomposition, procedural implementation, embedded systems, design methodology, memory optimization, Synchronous dataflow
1	Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit	Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs.	DAC	2007	DBLP DOI BibTeX RDF
1	Albert Meixner, Daniel J. Sorin	Error Detection Using Dynamic Dataflow Verification.	PACT	2007	DBLP DOI BibTeX RDF
1	Colin J. Ihrig, Justin Stander, Alex K. Jones	Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Najeem Lawal, Mattias O'Nils, Benny Thörnberg	C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Maarten Wiggers, Marco Bekooij, Pierre G. Jansen, Gerard J. M. Smit	Efficient Computation of Buffer Capacities for Cyclo-Static Real-Time Systems with Back-Pressure.	IEEE Real-Time and Embedded Technology and Applications Symposium	2007	DBLP DOI BibTeX RDF
1	Xiaoyong Chen, Douglas L. Maskell, Yang Sun	Fast Identification of Custom Instructions for Extensible Processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Bikash Agarwalla, Nova Ahmed, David Hilley, Umakishore Ramachandran	Streamline: scheduling streaming applications in a wide area environment.	Multimedia Syst.	2007	DBLP DOI BibTeX RDF
1	Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen	Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts.	ASAP	2006	DBLP DOI BibTeX RDF
1	John McAllister, Roger Woods, Richard L. Walke, D. Reilly	Multidimensional DSP Core Synthesis for FPGA.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	rapid implementation, field programmable gate array, heterogeneous system, system level design, dataflow graph, Architectural synthesis
1	Maarten Wiggers, Marco Bekooij, Pierre G. Jansen, Gerard J. M. Smit	Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	buffer capacity, system-on-chip, dataflow
1	Xiaoyong Chen, Douglas L. Maskell, Yang Sun	Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Gerson G. H. Cavalheiro, Epifanio Dinis Benitez, Daniela Saccol Peranconi, Eduardo Moschetta	Dynamic List Scheduling of Threads on Clusters.	CCGRID	2006	DBLP DOI BibTeX RDF
1	Lewis B. Baumstark Jr., Linda M. Wills	Multidimensional Dataflow-based Parallelization for Multimedia Instruction Set Extensions.	ICPP Workshops	2006	DBLP DOI BibTeX RDF
1	Vipin Swarup, Len Seligman, Arnon Rosenthal	Specifying Data Sharing Agreements.	POLICY	2006	DBLP DOI BibTeX RDF
1	Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya	Memory-constrained Block Processing Optimization for Synthesis of DSP Software.	ICSAMOS	2006	DBLP DOI BibTeX RDF
1	Ivan Corretjer, Chia-Jui Hsu, Shuvra S. Bhattacharyya	Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format.	SiPS	2006	DBLP DOI BibTeX RDF
1	Gregory H. Cooper, Shriram Krishnamurthi	Embedding Dynamic Dataflow in a Call-by-Value Language.	ESOP	2006	DBLP DOI BibTeX RDF
1	Vipin Swarup, Len Seligman, Arnon Rosenthal	A Data Sharing Agreement Framework.	ICISS	2006	DBLP DOI BibTeX RDF
1	Tsung-Hsi Chiang, Lan-Rong Dung, Ming-Feng Yaung	Modeling and formal verification of dataflow graph in system-level design using Petri net.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Vibhore Kumar, Brian F. Cooper, Zhongtang Cai, Greg Eisenhauer, Karsten Schwan	Resource-Aware Distributed Stream Management Using Dynamic Overlays.	ICDCS	2005	DBLP DOI BibTeX RDF
1	David Minor, Shmuel Rippa	GRAPE - An Industrial Distributed System for Computer Vision.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Lorenzo Verdoscia	CODACS Prototype: A Platform-Processor for CHIARA Programs.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke	Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System.	MICRO	2005	DBLP DOI BibTeX RDF
1	Nathan Clark, Hongtao Zhong, Scott A. Mahlke	Automated Custom Instruction Generation for Domain-Specific Processor Acceleration.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	instruction set interpretation, special-purpose, Automatic synthesis, special-purpose and application-based systems, instruction set design
1	Samir Jafar, Thierry Gautier, Axel W. Krings, Jean-Louis Roch	A Checkpoint/Recovery Model for Heterogeneous Dataflow Computations Using Work-Stealing.	Euro-Par	2005	DBLP DOI BibTeX RDF
1	Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler	Scalable selective re-execution for EDGE architectures.	ASPLOS	2004	DBLP DOI BibTeX RDF	EDGE architectures, load-store dependence prediction, mis-speculation recovery, selective re-execution, selective replay, speculative dataflow machines
1	Pan Yu, Tulika Mitra	Scalable custom instructions identification for instruction-set extensible processors.	CASES	2004	DBLP DOI BibTeX RDF	subgraph enumeration algorithm, ASIPs, instruction-set extensions, customizable processors
1	Magesh Sadasivam, Sangjin Hong	Dynamically reconfigurable architecture for high-throughput processing of data centric applications.	FPGA	2004	DBLP DOI BibTeX RDF
1	Bradley T. Vander Zanden, David K. Baker, Jing Jin	An explanation-based, visual debugger for one-way constraints.	UIST	2004	DBLP DOI BibTeX RDF	one-way constraints, data structures, constraint satisfaction, software visualization, visual debugging
1	Anne Bracy, Prashant Prahlad, Amir Roth	Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth.	MICRO	2004	DBLP DOI BibTeX RDF
1	Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim	Coupling-aware high-level interconnect synthesis [IC layout].	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya	Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition.	SCOPES	2004	DBLP DOI BibTeX RDF
1	Kubilay Atasu, Laura Pozzi, Paolo Ienne	Automatic application-specific instruction-set extensions under microarchitectural constraints.	DAC	2003	DBLP DOI BibTeX RDF	customisable processors, ASIPs, codesign, instruction-set extensions
1	Michael L. Chu, Kevin Fan, Scott A. Mahlke	Region-based hierarchical operation partitioning for multicluster processors.	PLDI	2003	DBLP DOI BibTeX RDF	multicluster processor, operation partitioning, clustering, instruction-level parallelism, instruction scheduling, region-based compilation
1	Rajnish Kumar, Matthew Wolenetz, Bikash Agarwalla, JunSuk Shin, Phillip W. Hutto, Arnab Paul, Umakishore Ramachandran	DFuse: a framework for distributed data fusion.	SenSys	2003	DBLP DOI BibTeX RDF	sensor network, middleware, data fusion, platform, energy awareness, in-network aggregation, role assignment
1	Michèl A. J. Rosien, Yuanqing Guo, Gerard J. M. Smit, Thijs Krol	Mapping Applications to an FPFA Tile.	DATE	2003	DBLP DOI BibTeX RDF
1	João M. P. Cardoso	On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	scheduling, FPGAs, reconfigurable computing, temporal partitioning
1	Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Michèl A. J. Rosien, Paul M. Heysters	Mapping Applications to a Coarse Grain Reconfigurable System.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
1	Kubilay Atasu, Laura Pozzi, Paolo Ienne	Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints.	International Journal of Parallel Programming	2003	DBLP DOI BibTeX RDF	customisable processors, automatic partitioning, hardware/software codesign, instruction-set extensions
1	Victor V. Toporkov	Decidability of the Analysis Problem for Dataflow Models of Programs.	Programming and Computer Software	2003	DBLP DOI BibTeX RDF
1	Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha	Efficient hardware controller synthesis for synchronous dataflow graph in system level design.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim	Coupling-aware high-level interconnect synthesis for low power.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh	Instruction generation for hybrid reconfigurable systems.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, high-level synthesis, reconfigurable computing
1	J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir	A Heuristic for Clock Selection in High-Level Synthesis.	VLSI Design	2002	DBLP DOI BibTeX RDF	clock selection, heuristics, high-level synthesis, design space exploration, graph structure
1	Lorenzo Verdoscia	CODACS Project: A Demand-Data Driven Reconfigurable Architecture (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
1	Ramaswamy Govindarajan, Guang R. Gao, Palash Desai	Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks.	VLSI Signal Processing	2002	DBLP DOI BibTeX RDF	buffer minimization, Digital Signal Processing (DSP) computation, Multi-Rate Software Pipelining, Regular Stream Flow Graphs, software pipelining, dataflow graphs
1	Brad T. Vander Zanden, Richard L. Halterman	Using model dataflow graphs to reduce the storage requirements of constraints.	ACM Trans. Comput.-Hum. Interact.	2001	DBLP DOI BibTeX RDF	Class-instance model, dataflow constraints, language design and implementation, prototype-instance model, storage optimization, programming environments, graphical interfaces
1	Euiseok Kim, Dong-Ik Lee	A new resource constrained asynchronous scheduling method through transformation of dataflow graphs.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm	An automated process for compiling dataflow graphs into reconfigurable hardware.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Marek Tudruj, Lukasz Masko	An Architecture and Task Scheduling Algorithm for Systems Based on Dynamically Reconfigurable Shared Memory Clusters.	IWCC	2001	DBLP DOI BibTeX RDF
1	Marek Tudruj, Lukasz Masko	Task Scheduling for Dynamically Configurable Multiple SMP Clusters Based on Extended DSC Approach.	PPAM	2001	DBLP BibTeX RDF
1	Marek Tudruj, Lukasz Masko	A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters.	PPAM	2001	DBLP BibTeX RDF
1	Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha	Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design.	ISSS	2000	DBLP DOI BibTeX RDF
1	Mark Stephenson, Jonathan Babb, Saman P. Amarasinghe	Bitwidth analysis with application to silicon compilation.	PLDI	2000	DBLP DOI BibTeX RDF
1	Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak	Optimizing computations for effective block-processing.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	computation dataflow graphs, scheduling, embedded systems, combinatorial optimization, high-level synthesis, vectorization, integer linear programming, retiming
1	Romain Kamdem, Alain Fonkoua	Coprocessor Synthesis of Multirate System Using Static Scheduling Theory. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	scheduling, real time, Codesign, codesign, hardware/software partitioning, target architecture
1	Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn	StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox.	FPL	2000	DBLP DOI BibTeX RDF
1	Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano	Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware.	FPL	2000	DBLP DOI BibTeX RDF
1	Thomas H. Drayer, Joseph G. Tront, Richard W. Conners, Philip A. Araman	A Development System for Creating Real-time Machine Vision Hardware using Field Programmable Gate Arrays. (PDF / PS)	HICSS	1999	DBLP DOI BibTeX RDF
1	Chanik Park, JaeWoong Chung, Soonhoi Ha	Extended Synchronous Dataflow for Efficient DSP System Prototyping. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	DSP system prototyping, Synchronous Dataflow
1	Henrik Tramberend	Avocado: A Distributed Virtual Reality Framework. (PDF / PS)	VR	1999	DBLP DOI BibTeX RDF
1	Volker Elling, Karsten Schwan	Min-Cut Methods for Mapping Dataflow Graphs.	Euro-Par	1999	DBLP DOI BibTeX RDF
1	Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee	Synthesis of Embedded Software from Synchronous Dataflow Specifications.	VLSI Signal Processing	1999	DBLP DOI BibTeX RDF
1	Wonyong Sung, Junedong Kim, Soonhoi Ha	Memory Efficient Software Synthesis from Dataflow Graph. (PDF / PS)	ISSS	1998	DBLP DOI BibTeX RDF
1	Freddy Gabbay, Avi Mendelson	Using Value Prediction to Increase the Power of Speculative Execution Hardware.	ACM Trans. Comput. Syst.	1998	DBLP DOI BibTeX RDF	stride value prediction, speculative execution, value prediction
1	Adrianos Lachanas, Paraskevas Evripidou	Exploiting Course Grain Parallelism from FORTRAN by Mapping it to IF1.	Euro-Par	1998	DBLP DOI BibTeX RDF
1	Min-You Wu, Wei Shu	On Parallelization of Static Scheduling Algorithms.	IEEE Trans. Software Eng.	1997	DBLP DOI BibTeX RDF	parallel scheduling algorithm, macro dataflow graph, modified critical-path algorithm, Static scheduling
1	Rachid Helaihel, Kunle Olukotun	Java as a specification language for hardware-software systems.	ICCAD	1997	DBLP DOI BibTeX RDF	java, Java, specification languages, hardware-software co-design
1	Clifford Beshers, Steven Feiner	Generating Efficient Virtual Worlds for Visualization Using Partial Evaluation and Dynamic Compilation.	PEPM	1997	DBLP DOI BibTeX RDF	multivariate data visualization, program transformation, virtual worlds, partial evaluation, dataflow
1	G. N. Srinivasa Prasanna	Compilation of Parallel Multimedia Computations - Extending Retiming Theory and Amdahl's Law.	PPOPP	1997	DBLP DOI BibTeX RDF
1	Steve Goddard	Analyzing the Real-Time Properties of a Dataflow Execution Paradigm using a Synthetic Aperture Radar Application. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1997	DBLP DOI BibTeX RDF
1	Michel Langevin, Eduard Cerny	A recursive technique for computing lower-bound performance of schedules.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	lower-bound on performance, microcode optimization, scheduling, resource constraints, dataflow graph