Search results for "decoupling capacitance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu	A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.	DAC	2006	DBLP DOI BibTeX RDF	sequence of linear programming, macromodeling, budgeting, decoupling capacitance
2	Thom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan	Statistical decoupling capacitance allocation by efficient numerical quadrature method.	ISQED	2009	DBLP DOI BibTeX RDF
2	Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He	Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Takashi Enami, Masanori Hashimoto, Takashi Sato	Decoupling capacitance allocation for timing with statistical noise model and timing analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
2	H. Yamamoto, J. A. Davis	Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan	On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.	DAC	2007	DBLP DOI BibTeX RDF
2	Sanjay Pant, David Blaauw	Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks.	ASP-DAC	2007	DBLP DOI BibTeX RDF
2	Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He	Efficient decoupling capacitance budgeting considering operation and process variations.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo	Floorplan-aware decoupling capacitance budgeting on equivalent circuit model.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman	On-die decoupling capacitance: frequency domain analysis of activity radius.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Sani R. Nassif, Kanak Agarwal, Emrah Acar	Methods for estimating decoupling capacitance of nonswitching circuit blocks.	ISCAS	2006	DBLP DOI BibTeX RDF
2	S. A. Moghaddam, N. Masoumi, Caro Lucas	A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance.	IWSOC	2005	DBLP DOI BibTeX RDF
2	Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera	Effects of on-chip inductance on power distribution grid.	ISPD	2005	DBLP DOI BibTeX RDF	on-chip inductance, power supply noise, power distribution network, decoupling capacitance
2	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh	Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh	Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Sudhakar Bobba, Ibrahim N. Hajj	Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Nathan Kalyanasundharam, Nital Patwa	Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor.	ICCD	1999	DBLP DOI BibTeX RDF	multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance
1	Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto	Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada	Decoupling capacitance boosting for on-chip resonant supply noise reduction.	DDECS	2011	DBLP DOI BibTeX RDF
1	Qing K. Zhu, Joe Yong, Tom Mozdzen	Decoupling capacitance study and optimization method for high-performance VLSIs.	DDECS	2010	DBLP DOI BibTeX RDF
1	Susumu Kobayashi, Naoshi Doi	An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles	An efficient decoupling capacitance optimization using piecewise polynomial models.	DATE	2009	DBLP BibTeX RDF
1	Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia	Decoupling capacitance efficient placement for reducing transient power supply noise.	ICCAD	2009	DBLP BibTeX RDF
1	Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar	Reducing peak power with a table-driven adaptive processor core.	MICRO	2009	DBLP DOI BibTeX RDF	resource resizing, voltage variation, peak power, adaptive architectures, decoupling capacitance
1	Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang	New spare cell design for IR drop minimization in Engineering Change Order.	DAC	2009	DBLP DOI BibTeX RDF	spare cell, IR drop, decoupling capacitor, ECO
1	Vasilis F. Pavlidis, Giovanni De Micheli	Power distribution paths in 3-D ICS.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	power distribution network, 3-D ICS, 3-D integration, through silicon vias
1	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Equivalent rise time for resonance in power/ground noise estimation.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.	ISQED	2008	DBLP DOI BibTeX RDF	signal integrity, mixed-signal circuits, Substrate coupling
1	Mikhail Popovich, Eby G. Friedman	Nanoscale on-chip decoupling capacitors.	SoCC	2008	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman	Effective Radii of On-Chip Decoupling Capacitors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu	Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu	Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity.	SoCC	2007	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs.	ICCAD	2007	DBLP DOI BibTeX RDF	power distribution grids, power noise, decoupling capacitors, power distribution systems
1	Anand Ramalingam, Giri Devarayanadurg, David Z. Pan	Accurate power grid analysis with behavioral transistor network modeling.	ISPD	2007	DBLP DOI BibTeX RDF	RC model of transistor, behavioral modeling of switch, power grid
1	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu	On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Timing-Aware Power-Noise Reduction in Placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Sanjay Pant, David Blaauw	An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks.	ICCD	2006	DBLP BibTeX RDF
1	Sarvesh H. Kulkarni, Dennis Sylvester	Power distribution techniques for dual VDD circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Mark M. Budnik, Kaushik Roy	Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network.	DATE	2006	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu	Maximum effective distance of on-chip decoupling capacitors in power distribution grids.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	power distribution grids, decoupling capacitors, power distribution systems
1	Jun Chen, Lei He	Noise driven in-package decoupling capacitor optimization for power integrity.	ISPD	2006	DBLP DOI BibTeX RDF	IC package, modeling, integrity, noise, power, resonance, decoupling capacitor, power distribution system
1	Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Mark M. Budnik, Kaushik Roy	A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Eric Wong, Jacob R. Minz, Sung Kyu Lim	Multi-Objective Module Placement For 3-D System-On-Package.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Toshio Sudo	Radiated Harmonics Characterization of CMOS Test Chip with On-Chip Decoupling Capacitance.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen	Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-based approach to fast on-chip decap budgeting and minimization.	DAC	2005	DBLP DOI BibTeX RDF	on-chi, power/grid networks, simulation, optimization, IR drop, decoupling capacitor
1	Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh	3D module placement for congestion and power noise reduction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	3D module placement, power noise reduction, congestion, system-on-package
1	Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda	Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.	ISQED	2005	DBLP DOI BibTeX RDF
1	Kai Wang, Malgorzata Marek-Sadowska	On-chip power-supply network optimization using multigrid-based technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Yiran Chen, Kaushik Roy, Cheng-Kok Koh	Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Yiran Chen, Kaushik Roy, Cheng-Kok Koh	Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda	DEPOGIT: dense power-ground interconnect architecture for physical design integrity.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Sani R. Nassif	The impact of variability on power.	ISLPED	2004	DBLP DOI BibTeX RDF	power, variability, integrated circuit
1	Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.	ISLPED	2004	DBLP DOI BibTeX RDF	integrated magnetics, on-die switching converter, power delivery, DC-DC converter, 3-D integration
1	Woo Hyung Lee, Sanjay Pant, David Blaauw	Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids.	ISQED	2004	DBLP DOI BibTeX RDF
1	Kai Wang, Malgorzata Marek-Sadowska	On-chip power supply network optimization using multigrid-based technique.	DAC	2003	DBLP DOI BibTeX RDF	congestion-aware, multigrid, power supply noise
1	Yiran Chen, Kaushik Roy, Cheng-Kok Koh	Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.	ISLPED	2003	DBLP DOI BibTeX RDF	power supply noise, inductive noise
1	Michael D. Powell, T. N. Vijaykumar	Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise.	ISLPED	2003	DBLP DOI BibTeX RDF	a priori current ramping, pipeline muffling, leakage, decoupling capacitors, inductive noise
1	Michael D. Powell, T. N. Vijaykumar	Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Li Yang, J. S. Yuan	Analyzing Internal-Switching Induced Simultaneous Switching Noise.	ISQED	2003	DBLP DOI BibTeX RDF
1	Sachin S. Sapatnekar, Haihua Su	Analysis and Optimization of Power Grids.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Onsi Fakhouri	Technology trends in power-grid-induced noise.	SLIP	2002	DBLP DOI BibTeX RDF	power grid noise
1	Pasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen	Interconnect peak current reduction for wavelet array processor using self-timed signaling.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi	Inductance model and analysis methodology for high-speed on-chip interconnect.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Juan Antonio Carballo, Sani R. Nassif	Impact of Technology in Power-Grid-Induced Noise.	PATMOS	2002	DBLP DOI BibTeX RDF
1	Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh	Decoupling capacitance allocation for power supply noise suppression.	ISPD	2001	DBLP DOI BibTeX RDF	interconnect sizing, power and ground network design, convex optimization
1	Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju	Model and analysis for combined package and on-chip power grid simulation.	ISLPED	2000	DBLP DOI BibTeX RDF