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Results
Found 10 publication records. Showing 10 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Nima Shahbazi, Hamid Sarbazi-Azad |
Accelerating 3-D capacitance extraction in deep sub-micron VLSI design using vector/parallel computing.  |
ICPADS  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | G. Razavipour, A. Motamedi, Ali Afzali-Kusha |
WL-VC SRAM: a low leakage memory circuit for deep sub-micron design.  |
ISCAS  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Saumil Shah, Puneet Gupta, Andrew B. Kahng |
Standard cell library optimization for leakage reduction.  |
DAC  |
2006 |
DBLP DOI BibTeX RDF |
gate-length biasing, library optimization, leakage reduction |
| 1 | Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty |
Managing standby and active mode leakage power in deep sub-micron design.  |
ISLPED  |
2004 |
DBLP DOI BibTeX RDF |
SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS |
| 1 | Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam |
Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic.  |
DSD  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Supratik Chakraborty, Rajeev Murgai |
Layout-Driven Timing Optimization by Generalized De Morgan Transform.  |
VLSI Design  |
2002 |
DBLP DOI BibTeX RDF |
layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure |
| 1 | Shih-Hsu Huang, Chu-Liao Wang |
An effective floorplan-based power distribution network design methodology under reliability constraints.  |
ISCAS  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Steffen Rochel, N. S. Nagaraj |
Full-Chip Signal Interconnect Analysis for Electromigration Reliability.  |
ISQED  |
2000 |
DBLP DOI BibTeX RDF |
Full-chip Analysis, Deep Sub-micron design, Validation, Electromigration |
| 1 | Yanhong Yuan, Prithviraj Banerjee |
Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. (PDF / PS)  |
ICCD  |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
Logic synthesis for large pass transistor circuits.  |
ICCAD  |
1997 |
DBLP DOI BibTeX RDF |
logic synthesis, BDD, Pass transistor logic |
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