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Searching for phrase deep sub-micron design (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1997-2007 (10)
Publication types (Num. hits)
inproceedings(10)
Venues (Conferences, Journals, ...)
ISCAS(2) DAC(1) DSD(1) ICCAD(1) ICCD(1) ICPADS(1) ISLPED(1) ISQED(1) VLSI Design(1)
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The graphs summarize 9 occurrences of 9 keywords

Results
Found 10 publication records. Showing 10 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Nima Shahbazi, Hamid Sarbazi-Azad Accelerating 3-D capacitance extraction in deep sub-micron VLSI design using vector/parallel computing. Search on Bibsonomy ICPADS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1G. Razavipour, A. Motamedi, Ali Afzali-Kusha WL-VC SRAM: a low leakage memory circuit for deep sub-micron design. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Saumil Shah, Puneet Gupta, Andrew B. Kahng Standard cell library optimization for leakage reduction. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF gate-length biasing, library optimization, leakage reduction
1Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty Managing standby and active mode leakage power in deep sub-micron design. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS
1Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. Search on Bibsonomy DSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Supratik Chakraborty, Rajeev Murgai Layout-Driven Timing Optimization by Generalized De Morgan Transform. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure
1Shih-Hsu Huang, Chu-Liao Wang An effective floorplan-based power distribution network design methodology under reliability constraints. Search on Bibsonomy ISCAS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Steffen Rochel, N. S. Nagaraj Full-Chip Signal Interconnect Analysis for Electromigration Reliability. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Full-chip Analysis, Deep Sub-micron design, Validation, Electromigration
1Yanhong Yuan, Prithviraj Banerjee Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. (PDF / PS) Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli Logic synthesis for large pass transistor circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF logic synthesis, BDD, Pass transistor logic
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