Search results for "delay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
7	W. Melody Moh, Yu-Jen Chien, Irene Zhang, Teng-Sheng Moh	Delay performance evaluation of high speed protocols for multimedia communications.	ICCCN	1995	DBLP DOI BibTeX RDF	delay performance evaluation, high speed protocols, delay fairness, worst-case delay performance, distributed queue dual bus, CRMA, cyclic reservation multiple access, DQMA, distributed queue multiple access, FDQ, fair distributed queue, heavy network load, reservation-based protocols, throughput, multimedia communication, multimedia communication, multimedia traffic, quality of service requirements, DQDB, access delay, message delay, heterogeneous traffic
6	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
6	Eun Sei Park, M. Ray Mercer, Thomas W. Williams	The Total Delay Fault Model and Statistical Delay Fault Coverage.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults
5	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults
5	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Safe Delay Optimization for Physical Synthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay
5	Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu	An Application-Independent Delay Testing Methodology for Island-Style FPGA.	DFT	2004	DBLP DOI BibTeX RDF	segment delay fault, FPGA, delay testing, path delay fault
5	Spyros Tragoudas, N. Denny	Path delay fault testing using test points.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	path delay fault simulation (coverage), testing digital circuits, design for testability, Automatic test pattern generation, delay testing, path delay fault testing
5	Maria K. Michael, Spyros Tragoudas	ATPG tools for delay faults at the functional level.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing
5	Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
5	Matthew K. H. Leung, John C. S. Lui, David K. Y. Yau	Characterization and Performance Evaluation for Proportional Delay Differentiated Services. (PDF / PS)	ICNP	2000	DBLP DOI BibTeX RDF	proportional delay differentiated services, Internet differentiated services, traffic classes, tariff rate, time-dependent priority scheduling, proportional delay model, delay ratios, scheduling parameters, efficient control algorithm, relative waiting time, performance evaluation, performance evaluation, Internet, delays, telecommunication traffic, waiting times, telecommunication services, ISP, feasible regions, average waiting time, service classes
5	Ping Zhou, Charles Thompson	Available Bit Rate (ABR) Source Control and Delay Estimation. (PDF / PS)	LCN	2000	DBLP DOI BibTeX RDF	nonlinear estimation, ABR source control, transmission rate regulation, ABR traffic source, linear quadratic rate regulation, round-trip propagation delay estimation, nonlinear least mean square, NLMS algorithm, ATM standard, asynchronous transfer mode, ATM network, simulation results, telecommunication traffic, least squares approximations, telecommunication control, delay estimation, delay estimation, available bit rate
5	Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee	Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis.	VTS	2000	DBLP DOI BibTeX RDF	delay defects, delay fault modeling, delay testing, critical paths, statistical timing analysis
5	Libin Dong, Rami G. Melhem, Daniel Mossé	Effect of scheduling jitter on end-to-end delay in TDMA protocols.	RTCSA	2000	DBLP DOI BibTeX RDF	scheduling jitter, TDMA protocols, time slot allocation algorithm, transmission rate, ETE delay bound, simulations, scheduling, distributed system, real-time systems, delays, time division multiple access, time division multiple access, jitter, real time communication, end-to-end delay, packet delay, destination node
5	Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro	Efficient Path Selection for Delay Testing Based on Path Clustering.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	clustering, delay testing, delay fault, path delay
5	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests
5	Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das	Delay Fault Coverage Enhancement Using Variable Observation Times.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	statistical delay fault coverage, delay test observation times, delay fault testing
5	Joseph Kee-Yin Ng, Shibin Song, Wei Zhao	Integrated delay analysis of regulated ATM switch. (PDF / PS)	IEEE Real-Time Systems Symposium	1997	DBLP DOI BibTeX RDF	integrated delay analysis, regulated ATM switch, worst case delay, hard real-time connection, real-time connection traffic, arrival functions, priority driven scheduling, FIFO scheduling, admission probability, cell delay estimation, performance, asynchronous transfer mode, deadline, simulation experiments, service functions, piecewise linear functions
5	Matthew Andrews, Antonio Fernández, Mor Harchol-Balter, Frank Thomson Leighton, Lisa Zhang	General Dynamic Routing with Per-Packet Delay Guarantees of O(distance + 1 / session rate).	FOCS	1997	DBLP DOI BibTeX RDF	per-packet delay, queue buildup, scheduling, packet-switching, communication networks, dynamic routing, telecommunication networks, performance guarantees, delay bounds, bursty traffic, packet delay, arbitrary topology
5	Mukund Sivaraman, Andrzej J. Strojwas	Timing analysis based on primitive path delay fault identification.	ICCAD	1997	DBLP DOI BibTeX RDF	primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing
5	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
5	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu	Analytical delay models for VLSI interconnects under ramp input.	ICCAD	1996	DBLP DOI BibTeX RDF	SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
5	Chung-Ping Chen, Hai Zhou, D. F. Wong	Optimal non-uniform wire-sizing under the Elmore delay model.	ICCAD	1996	DBLP DOI BibTeX RDF	Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation
5	Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal	Test Generation for Path Delay Faults Using Binary Decision Diagrams.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Boolean algebraic test generation, redundant delay faults, robust delay tests, scan testing of delay faults, binary decision diagrams, delay faults
5	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
5	Priyadarsan Patra, Donald S. Fussell	Power-efficient delay-insensitive codes for data transmission.	HICSS	1995	DBLP DOI BibTeX RDF	telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits
5	Wuudiann Ke, Premachandran R. Menon	Multifault testability of delay-testable circuits.	VTS	1995	DBLP DOI BibTeX RDF	delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
5	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
5	Daniel C. McCrackin	Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	deeply pipelined processors, delay enforced multistreaming, data dependency problem, jump problem, interdispatch delay, stream dispatching algorithms, modified fixed delay, encoded delay with fixed minimum, pipeline processing, processor architecture, interleaving, interlocks
4	Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Begueret	Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element
4	Quanxin Cheng, Haibo Bao, Jinde Cao	A Delay Fractioning Approach to Global Synchronization of Complex Networks with Distributed Delays and Stochastic Disturbances.	ISNN	2009	DBLP DOI BibTeX RDF	Global asymptotic synchronization, Delay fractioning, Stochastic disturbance, Distributed delay, Lyapunov functional
4	Qiufeng Cai, Jianjiang Yu	Further Stability Analysis for Neural Networks with Time-Varying Interval Delay.	ISNN	2009	DBLP DOI BibTeX RDF	Lyapunov-Krasovskii functional, Delay-dependent, Time-varying interval delay, Neural networks (NNs)
4	Praveen Jayachandran, Tarek F. Abdelzaher	Delay composition in preemptive and non-preemptive real-time pipelines.	Real-Time Systems	2008	DBLP DOI BibTeX RDF	Pipelined distributed systems, Delay composition, Schedulability, End-to-end delay
4	Minjin Zhang, Huawei Li, Xiaowei Li	Multiple Coupling Effects Oriented Path Delay Test Generation.	VTS	2008	DBLP DOI BibTeX RDF	crosstalk, delay test, path delay fault
4	Yu Wang, Hongyi Wu	Delay/Fault-Tolerant Mobile Sensor Network (DFT-MSN): A New Paradigm for Pervasive Information Gathering.	IEEE Trans. Mob. Comput.	2007	DBLP DOI BibTeX RDF	Delay/fault-tolerant mobile sensor network, delivery delay, delivery probability, DFT-MSN, pervasive information gathering, transmission overhead, replication, queuing theory, erasure coding
4	S. Dabas, Ning Dong, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
4	Tien-Ting Fang, Ting-Chi Wang	Fast Buffered Delay Estimation Considering Process Variations.	ASP-DAC	2007	DBLP DOI BibTeX RDF	statistical buffer insertion method, buffered delay estimation, first-order canonical forms, buffer blockages, deterministic delay estimation method, process variations
4	Ioannis Papapanagiotou, John S. Vardakas, Georgios S. Paschos, Michael D. Logothetis, Stavros A. Kotsopoulos	Performance evaluation of IEEE 802.11e based on ON-OFF traffic model.	MobiMedia	2007	DBLP DOI BibTeX RDF	MAC delay, QoS, IEEE 802.11e, end-to-end delay, queuing delay
4	Omer Gurewitz, Israel Cidon, Moshe Sidi	One-way delay estimation using network-wide measurements.	IEEE Transactions on Information Theory	2006	DBLP DOI BibTeX RDF	network measurements, maximum entropy, delay estimation, mathematical optimization, one-way delay
4	Heejin Lim, Yoonsuck Choe	Facilitating neural dynamics for delay compensation and prediction in evolutionary neural networks.	GECCO	2006	DBLP DOI BibTeX RDF	delay compensation, facilitating synapses, neural delay, pole balancing, extrapolation, evolutionary neural networks
4	Baris Bozkurt, Thierry Dutoit, Laurent Couvreur	Spectral Analysis of Speech Signals Using Chirp Group Delay.	WNSP	2005	DBLP DOI BibTeX RDF	Phase processing, chirp group delay, group delay, zzt, ASR feature extraction
4	Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	Path delay test compaction with process variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	process variation, delay testing, path delay fault, test compaction
4	Hagit Attiya, David Hay	The inherent queuing delay of parallel packet switches.	SPAA	2004	DBLP DOI BibTeX RDF	leaky-bucket traffic, load balancing, packet switching, clos networks, queuing delay, delay jitter, inverse multiplexing
4	Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak	Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.	DAC	2003	DBLP DOI BibTeX RDF	delay ATPG, delay fault diagnosis, statistical timing models
4	Muhammad Nummer, Manoj Sachdev	A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	high-performance testing, controlled-delay flip-flop, built-in self test, delay-fault testing, design for delay testability
4	Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On Selecting Testable Paths in Scan Designs.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	testable path, delay testing, delay fault, path delay fault, path selection
4	Luís Guerra e Silva, João P. Marques Silva, Luis Miguel Silveira, Karem A. Sakallah	Satisfiability models and algorithms for circuit delay computation.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	circuit delay computation, timing analysis, Boolean satisfiability, delay modeling, false path
4	Yasuyoshi Yokokohji, Teruhiro Tsujioka, Tsuneo Yoshikawa	Bilateral Control with Time-Varying Delay Including Communication Blackout.	Symposium on Haptic Interfaces for Virtual Environment and Teleoperator Systems	2002	DBLP DOI BibTeX RDF	master-slave manipulator, the Internet, computer network, teleoperation, time delay, time-varying delay, bilateral control
4	Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev	Design for Delay Testability in High-Speed Digital ICs.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	BIST, delay-fault testing, design for delay testability, high-speed testing
4	Huawei Li, Zhongcheng Li, Yinghua Min	Reduction of Number of Paths to be Tested in Delay Testing.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	linearly independent, analytical delay model, delay testing, path sensitization
4	Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi	False-Path Removal Using Delay Fault Simulation.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal
4	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
4	Yu-Sheng Huang, Chih-wen Hsueh	Minimizing the maximum end-to-end delay on tree structure using the distributed pinwheel model.	RTCSA	2000	DBLP DOI BibTeX RDF	maximum end-to-end delay minimisation, distributed pinwheel model, end-to-end timing requirements, tight maximum delay bound, quality of service, Internet, computational complexity, timing, computer networks, heuristic algorithm, processor scheduling, timing constraints, simulation result, distributed real-time systems, tree structure, heuristic programming, NP-hard problems, linear-time algorithm, pipeline structure
4	Maria Teresa Andrade, Artur Pimenta Alves	Experiments with Dynamic Multiplexing and UPC Renegotiation for Video over ATM.	NETWORKING	2000	DBLP DOI BibTeX RDF	renegotiation Abbreviations: AAL, ATM Adaptation Layer, ACTS, Advanced Communications, Technologies & Services, CDV, Cell Delay Variation, CDVT, Cell Delay Variation Tolerance, CTD, Cell Transfer Delay, EFCI, Explicit Forward Congestion Indication, GOP, Group Of Pictures, MBS, Maximum Burst Size, Motion Picture Expert Group, Network Interface Card, Peak Cell Rate, MCR, Minimum Cell Rate, Resource and Management, Sustainable Cell Rate, UNI, User Network Interface, Usage Parameter Control, Quality of Service, QoS, Quality of Service, ATM, ATM, Asynchronous Transfer Mode, VoD, Video on Demand, CAC, MPEG, CBR, statistical multiplexing, VBR, Variable Bit Rate, Connection Admission Control, UPC, UPC, ABR, Virtual Circuit, RM, Available Bit Rate, SCR, PCR, VC, NIC, Constant Bit Rate
4	Irith Pomeranz, Sudhakar M. Reddy	Vector-Based Functional Fault Models for Delay Faults.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	functional tests, delay faults, path delay faults
4	Shibin Song, Joseph Kee-Yin Ng, Bihai Tang	Statistical Delay Analysis with Self-Similar Input Traffic in ATM Networks.	RTCSA	1999	DBLP DOI BibTeX RDF	Real-Time ATM Networks, Statistical Delay Analysis, Efficient Delay Computation, Performance Evaluation, Self-similar Traffic
4	Shibin Song, Joseph Kee-Yin Ng, Bihai Tang	Efficient Delay Computation Methods for an ATM Network with Real-Time Video Traffic. (PDF / PS)	IEEE Real-Time Systems Symposium	1999	DBLP DOI BibTeX RDF	Real-Time ATM Networks, Worst Case Delay Analysis, Efficient Delay Computation, Performance Evaluation
4	Moonsoo Kang, Chansu Yu	Job-Based Queue Delay Modeling in a Space-Shared Hypercube. (PDF / PS)	ICPP Workshops	1999	DBLP DOI BibTeX RDF	topological delay, processor allocation, space sharing, queue delay, Hypercube computer
4	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
4	Zhongcheng Li, Yinghua Min, Robert K. Brayton	A New Low-Cost Method for Identifying Untestable Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF	non-robustly untestable, Delay testing, path delay fault, implication
4	Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal	Path Delay Testing: Variable-Clock Versus Rated-Clock.	VLSI Design	1998	DBLP DOI BibTeX RDF	rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test
4	Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas	C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays
4	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	digital circuit testing, test generation, fault models, delay test, path delay faults
4	Angela Krstic, Kwang-Ting Cheng	Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing
4	Jacob Savir	Delay Test Generation: A Hardware Perspective.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	transition test, skewed-load delay test, shift dependency, cellular automata, linear feedback shift register, delay test, pseudo-random test
4	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga	A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	marginal delay, test generation, combinational circuit, gate delay faults
4	Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto	Application of a Design for Delay Testability Approach to High Speed Logic LSIs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Delay Test Generation, Design for Testability, Delay Testing
4	Sreejit Chakravarty	On the capability of delay tests to detect bridges and opens.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	defective IC, faulty dynamic logic behavior, transition tests, simulation, integrated circuit testing, delay tests, bridges, opens, at-speed testing, path delay tests
4	Xiaoming Yu, Yinghua Min	Design of delay-verifiable combinational logic by adding extra inputs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	delay-verifiable combinational logic, delay testability, synthesis, combinational circuits, hardware overhead, temporal behavior
4	Xiaohua Jia, Niki Pissinou, Kia Makki	A distributed algorithm of delay bounded multicast routing for multimedia applications.	ICCCN	1997	DBLP DOI BibTeX RDF	delay bounded multicast routing, source node, multicast destinations, distributed heuristic algorithm, sub-optimal network cost, delay bound constraint, multicast membership changes, simulations, delays, multimedia applications, routing trees
4	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
4	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial scan delay fault testing of asynchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	robust path delay fault testing, asynchronous circuits, delay faults, sequential testing
4	Maggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillinger, David P. LaPotin	Delay bounded buffered tree construction for timing driven floorplanning.	ICCAD	1997	DBLP DOI BibTeX RDF	Total Wire Length, DBB-tree, SPT, Floorplanning, Buffer Insertion, Delay Bounds, Elmore Delay, MST
4	William Perrizo, Zhili Zhang, Stephen Krebsbach	Strategies for implementing distributed query algorithms over high-speed, bandwidth-on-demand, wide area networks. (PDF / PS)	COMPSAC	1997	DBLP DOI BibTeX RDF	high-speed bandwidth-on-demand wide area networks, distributed query processing algorithms, latency delay reduction, multicast issue handling, transmission delay reduction, local processing delay reduction, distributed join algorithm, time cost, near optimal performance, distributed databases, analytical model, distributed database systems
4	Lei Wang 0014, Carl McCrosky	Performance Comparison of Control Schemes for ABR Service in ATM LANs.	MASCOTS	1997	DBLP DOI BibTeX RDF	ABR service, ATM Forum, available bit rate service, constrained cell loss, network resource utilization, CBR/VBR services, burst level traffic control, rate based feedback control, loss sensitive applications, delay insensitive applications, burst transfer delay, simulation, asynchronous transfer mode, bandwidth, performance comparison, ATM LAN, delay variation
4	Chengzhi Li, Riccardo Bettati, Wei Zhao	Static priority scheduling for ATM networks. (PDF / PS)	IEEE Real-Time Systems Symposium	1997	DBLP DOI BibTeX RDF	dynamic priority scheduling, delay computation, priority assignment problems, potential cyclic dependency, unstable network, delay sensitive applications, worst case end to end delays, priority assignment methods, asynchronous transfer mode, ATM networks, numerical method, ATM switches, packet delays, arbitrary topology, delay constraints, priority assignment, traffic scheduling, static priority scheduling, computing error
4	Yuan-Chieh Hsu, Sandeep K. Gupta	A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	robust path delay testing, at-speed delay testing, fault simulation, Delay testing
4	Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang	Cell delay fault testing for iterative logic arrays.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	cell delay fault, path delay fault, C-testable, iterative logic array, pseudoexhaustive testing
4	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
4	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
4	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Segment delay faults: a new fault model.	VTS	1996	DBLP DOI BibTeX RDF	segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects
4	Mukund Sivaraman, Andrzej J. Strojwas	A diagnosability metric for parametric path delay faults.	VTS	1996	DBLP DOI BibTeX RDF	diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
4	Yinghua Min, Zhuxing Zhao, Zhongcheng Li	An Analytical Delay Model Based on Boolean Process.	VLSI Design	1996	DBLP DOI BibTeX RDF	waveform polynomial, transition delay, floating delay, sensitization, Boolean process
4	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	On test coverage of path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
4	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Parallel concurrent path-delay fault simulation using single-input change patterns.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations
4	H. Bekker, E. J. Dijkstra	Delay-Insensitive Synchronization on a Message-Passing Architecture with an Open Collector Bus.	PDP	1996	DBLP DOI BibTeX RDF	delay-insensitive synchronization, open collector bus, high latency, constraint algorithm, SHAKE, Constraint Molecular Dynamics simulation, ring architecture, delay insensitive algorithm, performance evaluation, performance, parallel algorithms, parallel algorithms, parallel architectures, message passing, multiprocessor interconnection networks, multiprocessor interconnection networks, synchronisation, digital simulation, physics computing, system buses, communication time, message passing architecture
4	Mukund Sivaraman, Andrzej J. Strojwas	Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults.	ICCAD	1996	DBLP DOI BibTeX RDF	fabrication process, coverage, delay testing, delay fault, path sensitization
4	Syed Sohel Hussain, Yih-Chyun Jenq	Analysis and Optimization of a Banyan-Based ATM Switch by Simulations. (PDF / PS)	LCN	1996	DBLP DOI BibTeX RDF	Banyan based ATM switch, switch optimization, switch analysis, delay variance, performanc analysis, uniform traffic, three-state model, nonblocking first stage, packet blocking, enhanced priority scheme, single buffer Banyan network, double buffer switching element, delay sensitive voice packet, asynchronous transfer mode, asynchronous transfer mode, delay, throughput, bandwidth, simulation results, voice traffic, data traffic
4	Ankan K. Pramanick, Sudhakar M. Reddy	Efficient multiple path propagating tests for delay faults.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	delay testing, path delay faults, robust tests, test efficiency
4	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
4	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu	Generation of tenacious tests for small gate delay faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
4	Wen Ching Wu, Chung-Len Lee, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
4	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	Diagnostic of path and gate delay faults in non-scan sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
4	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Statistical methods for delay fault coverage analysis.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
4	Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao	Bounded-skew clock and Steiner routing under Elmore delay.	ICCAD	1995	DBLP DOI BibTeX RDF	bounded-skew, pathlength delay, VLSI, global routing, Elmore delay, zero-skew, zero-skew, clock routing, routing trees
4	Shashidhar Thakur, D. F. Wong	Simultaneous area and delay minimum K-LUT mapping for K-exact networks. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	area/delay minimum K-LUT mapping, K-exact networks, technology mapping problem, lookup table FPGAs, area minimization problem, K-bounded networks, delay minimization problem, flow-map algorithm, field programmable gate arrays, computational complexity, complexity, NP-complete, logic design, polynomial time algorithm, programmable logic arrays, table lookup, minimisation of switching nets
3	Sumet Prabhavat, Hiroki Nishiyama, Nirwan Ansari, Nei Kato	Effective Delay-Controlled Load Distribution over Multipath Networks.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	multipath forwarding, packet delay variation, load distribution, Delay minimization, packet reordering
3	Tahir Nawaz Minhas, Markus Fiedler, Patrik Arlos	Quantification of packet delay variation through the coefficient of throughput variation.	IWCMC	2010	DBLP DOI BibTeX RDF	coefficient of throughput variation, network measurement traffice shapping, packet delay variation, traffic shaper, performance analysis, throughput
3	Nesrine Ouferhat, Abdelhamid Mellouk	Inductive routing based on energy and delay metrics in wireless sensor networks.	IWCMC	2010	DBLP DOI BibTeX RDF	multi criteria routing optimization, state dependent algorithm, QoS, Delay, energy consumption
3	Mohammed Al-Siyabi, Haitham S. Cruickshank, Zhili Sun	Quality of service provisioning for delay tolerant network by implementing admission control model for aircrafts bundles data transmission.	IWCMC	2010	DBLP DOI BibTeX RDF	aircraft and admission control (AC), quality of service (QoS), delay tolerant network (DTN)