Search results for "delay element"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Colin J. Ihrig, Gerold Joseph Dhanabalan, Alex K. Jones	A low-power CMOS thyristor based delay element with programmability extensions.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay element, thyristor, low power
2	Hooman Farkhani, Mohammad Maymandi-Nejad, Manoj Sachdev	A fully digital ADC using a new delay element with enhanced linearity.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Srivathsan Krishnamohan, Nihar R. Mahapatra	An analysis of the robustness of CMOS delay elements.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	delay element, process variation, yield, Monte Carlo simulation
2	Junmou Zhang, Simon R. Cooper, Andrew R. LaPietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman	A low power thyristor-based CMOS programmable delay element.	ISCAS	2004	DBLP DOI BibTeX RDF
2	Mohammad Maymandi-Nejad, Manoj Sachdev	A digitally programmable delay element: design and analysis.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Soo-Chang Pei, Yun-Da Huang, Shih-Hsin Lin, Jong-Jy Shyu	Design of variable comb filter using FIR variable fractional delay element.	Signal Processing	2012	DBLP DOI BibTeX RDF
1	Jun Xu, Xiangku Li	Improve accuracy of delay element by filtering false path for low power desychronized circuits.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Louis H. Jung, Torsten Lehmann, Gregg J. Suaning, Nigel H. Lovell	A semi-static threshold-triggered delay element for low power applications.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Faramarz Asharif, Shiro Tamaki, Tsutomu Nagado, Nagata Tomokazu, Mohammad Reza Alsharif	Application of Internal Model Controller for Wind Turbine System Considering Time-delay Element.	ICINCO	2011	DBLP BibTeX RDF
1	Mariya Kurchuk, Yannis P. Tsividis	Energy-efficient asynchronous delay element with wide controllability.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Jung-Lin Yang, Chih-Wei Chao	Ultra Low Power Delay Element with Post-Chip Adjustable Ability.	IEICE Transactions	2009	DBLP BibTeX RDF
1	P. V. Manjunath, H. R. Baghyalakshmi, M. K. Venkatesha	A Low-Power Low-Voltage CMOS Thyristor Based Delay Element.	ICETET	2009	DBLP DOI BibTeX RDF
1	Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Begueret	Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element
1	Hong Nie, Zhizhang Chen	Code-Shifted Reference Ultra-Wideband (UWB) Radio.	CNSR	2008	DBLP DOI BibTeX RDF	transmitted reference, code-shifted reference, Walsh code, Ultra-wideband, impulse radio
1	Mahdi Fazeli, Seyed Ghassem Miremadi	A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.	DFT	2008	DBLP DOI BibTeX RDF
1	Jyh-Horng Wen, Hsi-Chou Hsu, Po-Wei Chen	Parallel Signal Acquisition in Ultra-Wideband Systems with Shared Looped Delay-Line.	ICC	2008	DBLP DOI BibTeX RDF
1	Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang	A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Wei Teng, Yunfei Zhou, Xiaoqing Li, Liangliang Yang	Design of Acceleration Feedforward and Study of Calibration Algorithm.	ICIRA	2008	DBLP DOI BibTeX RDF	Acceleration feedforward, Feedforward coefficient, Calibration algorithm, Delay time
1	Yanlong Zhang, Zhiping Wen, Lixin Yu	Design and Analysis of a Modified Digitally Controlled Programmable Delay Element.	IMECS	2007	DBLP BibTeX RDF
1	Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks	On-chip samplers for test and debug of asynchronous circuits.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Ming-Hung Chang, Zong-Xi Yang, Wei Hwang	A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Dennis Goeckel, Qu Zhang	Slightly Frequency-Shifted Reference Ultra-Wideband (UWB) Radio.	IEEE Transactions on Communications	2007	DBLP DOI BibTeX RDF
1	Bakhtiar Affendi Rosdi, Atsushi Takahashi	Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Jianwei Zhang, Yizheng Ye, Bin-Da Liu	A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Luis Nero Alves, Luis Barbosa, E. A. L. Macedo, Rui L. Aguiar	General model for delayed feedback and its application to transimpedance amplifier's bandwidth optimization.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Afshin Haftbaradaran, Kenneth W. Martin	Mismatch compensation techniques using random data for time-interleaved A/D converters.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Luis Nero Alves, Rui L. Aguiar	On the effect of time delays in negative feedback amplifiers.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Mohammad Maymandi-Nejad, Manoj Sachdev	Correction to "A Digitally Programmable Delay Element: Design and Analysis".	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida	Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Shih-Lien Lu	Implementation of micropipelines in enable/disable CMOS differential logic.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
1	Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King	MULTIPAR: behavioral partition for synthesizing multiprocessor architectures.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF