Search results for "delay optimization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect power and delay optimization by dynamic programming in gridded design rules.	ISPD	2010	DBLP DOI BibTeX RDF	gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
2	Alan Mishchenko, Robert K. Brayton, Stephen Jang	Global delay optimization using structural choices.	FPGA	2010	DBLP DOI BibTeX RDF	technology mpping, FPGA, interpolation, windowing, boolean satisfiability, logic optimization
2	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Power-delay optimization in VLSI microprocessors by wire spacing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Wire spacing, power optimization, interconnect optimization, delay-optimization
2	Hiran Tennakoon, Carl Sechen	Nonconvex Gate Delay Modeling and Delay Optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Slimane Ben Slimane, Xuesong Li, Bo Zhou, Nauroze Syed, Mohammad Abu Dheim	Delay Optimization in Cooperative Relaying with Cyclic Delay Diversity.	ICC	2008	DBLP DOI BibTeX RDF
2	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Safe Delay Optimization for Physical Synthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay
2	Sang-Chul Kim	An End-to-End Packet Delay Optimization for QoS in a MANET.	ICESS	2007	DBLP DOI BibTeX RDF
2	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Dominator-based partitioning for delay optimization.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	logic design, timing optimization, logic partitioning
2	Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang	Minimum delay optimization for domino circuits - a coupling-aware approach.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Logic synthesis, coupling, domino logic, delay minimization
2	Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang	Coupling-aware minimum delay optimization for domino logic circuits.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Buffer insertion for noise and delay optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Maitham Shams, Mohamed I. Elmasry	Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions.	ICCD	1999	DBLP DOI BibTeX RDF
2	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Buffer Insertion for Noise and Delay Optimization.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
2	Bradley S. Carlson, Suh-Juch Lee	Delay optimization of digital CMOS VLSI circuits by transistor reordering.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Jason Cong, Yuzheng Ding	FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar	DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.	IEEE Design & Test of Computers	1992	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	The complexity of VLSI power-delay optimization by interconnect resizing.	J. Comb. Optim.	2012	DBLP DOI BibTeX RDF
1	Mahdi Mahdi Khodaian, Jesus Perez, Babak Hossein Khalaj, Pedro M. Crespo	Adaptive access and rate control of CSMA for energy, rate, and delay optimization.	EURASIP J. Wireless Comm. and Networking	2012	DBLP DOI BibTeX RDF
1	Ming Xiao, Muriel Médard, Tor Aulin	Cross-Layer Design of Rateless Random Network Codes for Delay Optimization.	IEEE Transactions on Communications	2011	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Delay optimization considering power saving in dynamic CMOS circuits.	ISQED	2011	DBLP DOI BibTeX RDF
1	D. S. Harish Ram, M. C. Bhuvaneswari, S. M. Logesh	A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Reuven Cohen, Boris Kapchits	Energy-delay optimization in an asynchronous sensor network with multiple gateways.	SECON	2011	DBLP DOI BibTeX RDF
1	Mohammadhossein Alvandi, Mustafa Mehmet-Ali, Jeremiah F. Hayes	Delay optimization of wireless networks with network coding.	CCECE	2011	DBLP DOI BibTeX RDF
1	Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets	Delay optimization using SOP balancing.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Ahmed M. Mahdy, Jitender S. Deogun	Adaptive Optical Wireless Networks: End-to-End Link Delay Optimization.	JCIT	2010	DBLP BibTeX RDF
1	Miguel P. Pereira, Luis Bernardo, Rui Dinis, Rodolfo Oliveira, Paulo Carvalho, Paulo Pinto	Delay Optimization on a p-Persistent MAC Protocol for a Multi-Packet Detection in SC-FDE System.	WCNC	2010	DBLP DOI BibTeX RDF
1	Ming Xiao	Cross-Layer Design of Rateless Random Network Codes for Delay Optimization.	ICC	2010	DBLP DOI BibTeX RDF
1	Francesco Chiti, Romano Fantacci, Dejan Vukobratovic	Joint Discrete Power-Level and Delay Optimization for Network Coded Wireless Communications.	ICC	2010	DBLP DOI BibTeX RDF
1	Levent Aksoy, Diego Jaccottet, Eduardo Costa	Design of low complexity digital FIR filters.	SBCCI	2009	DBLP DOI BibTeX RDF	low-level synthesis, multiple constant multiplications, multiplierless filter design, high-level synthesis, array multipliers
1	Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam	Variation-aware multimetric optimization during gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise
1	Petar Djukic, Shahrokh Valaee	Delay aware link scheduling for multi-hop TDMA wireless networks.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	TDMA scheduling algorithms, scheduling delay, stop-and-go queueing
1	Slimane Ben Slimane, Bo Zhou, Xuesong Li	Delay Optimization in Cooperative Relaying with Cyclic Delay Diversity.	EURASIP J. Adv. Sig. Proc.	2008	DBLP DOI BibTeX RDF
1	Massimo Alioto, Gaetano Palumbo	Power-delay optimization in MCML tapered buffers.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Ghalem Boudour, Cédric Teyssié, Zoubir Mammeri	Scheduling-Based Reservation MAC Protocol for Bandwidth and Delay Optimization in Wireless Mesh Networks.	WiMob	2008	DBLP DOI BibTeX RDF
1	Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw	On the decreasing significance of large standard cells in technology mapping.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs.	ISQED	2008	DBLP DOI BibTeX RDF
1	Josep Carmona, Jordi Cortadella	Encoding Large Asynchronous Controllers With ILP Techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Suhas N. Diggavi, A. Robert Calderbank, Sanket Dusad, Naofal Al-Dhahir	Diversity Embedded Space-Time Codes.	IEEE Transactions on Information Theory	2008	DBLP DOI BibTeX RDF
1	Ahmad Al Hanbali, Roland de Haan, Richard J. Boucherie, Jan-Kees C. W. van Ommeren	A Tandem Queueing Model for Delay Analysis in Disconnected Ad Hoc Networks.	ASMTA	2008	DBLP DOI BibTeX RDF	Tandem queueing model, Autonomous server, Ad hoc networks, Performance analysis, Delay-tolerant networking
1	Shuguang Cui, Ritesh Madan, Andrea J. Goldsmith, Sanjay Lall	Cross-Layer Energy and Delay Optimization in Small-Scale Sensor Networks.	IEEE Transactions on Wireless Communications	2007	DBLP DOI BibTeX RDF
1	Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava	Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Samuli Aalto, Urtzi Ayesta	Mean delay optimization for the M/G/1 queue with pareto type service times.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	gittins index, scheduling, pareto distribution, M/G/1, mean delay
1	Jeong-Gun Lee, Jeong-A. Lee, Byeong-Seok Lee, Milos D. Ercegovac	A Design Method for Heterogeneous Adders.	ICESS	2007	DBLP DOI BibTeX RDF
1	Dieter Rautenbach, Christian Szegedy, Jürgen Werber	Delay optimization of linear depth boolean circuits with prescribed input arrival times.	J. Discrete Algorithms	2006	DBLP DOI BibTeX RDF
1	Joey Y. Lin, Deming Chen, Jason Cong	Optimal simultaneous mapping and clustering for FPGA delay optimization.	DAC	2006	DBLP DOI BibTeX RDF	clustering, FPGA, dynamic programming, technology mapping
1	Ahmed Bader, Eylem Ekici	Throughput and delay optimization in interference-limited multihop networks.	MobiHoc	2006	DBLP DOI BibTeX RDF	link model, optimization, multihop networks, fading
1	Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro	Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming.	DAC	2006	DBLP DOI BibTeX RDF	multiple constant multiplication, multiplierless digital filter design, delay optimization, area optimization
1	Maaike Verloop, Rudesindo Núñez-Queija, Sem C. Borst	Delay-optimal scheduling in bandwidth-sharing networks.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	alpha-fair strategies, bandwidth-sharing networks, delay optimization
1	Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny	Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan	A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Jean-Paul Wagner, Pascal Frossard	Playback Delay Optimization in Scalable Video Streaming.	ICME	2005	DBLP DOI BibTeX RDF
1	Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan	ADOPT: An Approach to Activity Based Delay Optimization.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Yunfeng Wang, Jinian Bian, Xianlong Hong	Interconnect delay optimization via high level re-synthesis after floorplanning.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Eduardo Parente Ribeiro, Victor C. M. Leung	Asymmetric path delay optimization in mobile multi-homed SCTP multimedia transport.	WMuNeP	2005	DBLP DOI BibTeX RDF	asymmetric path, multimedia, delay, mobile network, SCTP, multi-homing
1	Guang Tan, Stephen A. Jarvis, Xinuo Chen, Daniel P. Spooner, Graham R. Nudd	Performance Analysis and Improvement of Overlay Construction for Peer-to-Peer Live Media Streaming.	MASCOTS	2005	DBLP DOI BibTeX RDF
1	Yibo Wang, Yici Cai, Xianlong Hong	A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.	VLSI Design	2005	DBLP DOI BibTeX RDF	accurate delay model, obstacle-aware routing, buffer insertion, interconnect optimization
1	Yuanzhong Wan, Maitham Shams	Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Timing-driven partitioning-based placement for island style FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang	A predictive distributed congestion metric with application to technology mapping.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Ahmed M. Mahdy, Jitender S. Deogun, Shashank K. Mehta	Broadband Optical Wireless Internet: Delay Optimization.	BROADNETS	2004	DBLP DOI BibTeX RDF
1	Peter-Michael Seidel, Guy Even	Delay-Optimized Implementation of IEEE Floating-Point Addition.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition
1	Mongkol Ekpanyapong, Sung Kyu Lim	Performance-driven global placement via adaptive network characterization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Baruch Awerbuch, Robert D. Kleinberg	Adaptive routing with end-to-end feedback: distributed learning and geometric approaches.	STOC	2004	DBLP DOI BibTeX RDF	multi-armed bandit problem, online decision problem, online linear optimization, routing
1	Olivier Peyran, Zheng Zeng, Wenjun Zhuang	Area optimization of delay-optimized structures using intrinsic constraint graphs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Xuemin Lin	Delay Optimization in Quorum Consensus.	Algorithmica	2003	DBLP DOI BibTeX RDF	Optimizations, Quorum consensus, Replicated data management
1	Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang	Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Fast timing-driven partitioning-based placement for island style FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGA placement, partitioning based placement, FPGAs, timing-driven placement
1	Shrutin Ulman	Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne	Design Techniques for EEPROMs Embedded in Portable Systems on Chips.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Matthias Müller-Hannemann, Ute Zimmermann	Slack Optimization of Timing-Critical Nets.	ESA	2003	DBLP DOI BibTeX RDF
1	Paul I. Pénzes, Alain J. Martin	Energy-delay efficiency of VLSI computations.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	energy-delay optimization, transistor sizing
1	Paul I. Pénzes, Mika Nyström, Alain J. Martin	Transistor sizing of energy-delay--efficient circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	energy-delay optimization, transistor sizing
1	Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang	Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.	DAC	2001	DBLP DOI BibTeX RDF
1	Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang	Performance-driven mapping for CPLD architectures.	FPGA	2001	DBLP DOI BibTeX RDF	PLA-style logic cells, FPGA, technology mapping, CPLD, delay optimization
1	Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh	On the complexity of gate duplication.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Javed I. Khan	Active Streaming in Transport Delay Minimization. (PDF / PS)	ICPP Workshops	2000	DBLP DOI BibTeX RDF	proactive Internet caching, Multimedia, streaming, pre-fetching, delay optimization
1	Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne	Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions.	MTDT	2000	DBLP DOI BibTeX RDF
1	Jason Cong, Songjie Xu	Performance-driven technology mapping for heterogeneous FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Mukund Sivaraman, Andrzej J. Strojwas	Primitive path delay faults: identification and their use in timinganalysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens	Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.	ICCAD	1999	DBLP BibTeX RDF
1	Yutaka Tamiya	Performance optimization using separator sets.	ICCAD	1999	DBLP BibTeX RDF
1	José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías	Logic Restructuring for MUX-Based FPGAs.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	Noel Menezes, Chung-Ping Chen	Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Tohru Ishihara, Hiroto Yasuura	Voltage scheduling problem for dynamically variable voltage processors.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Martin Paterok	Delay Optimization for Spanning Tree Networks.	MMB	1997	DBLP BibTeX RDF
1	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
1	Mukund Sivaraman, Andrzej J. Strojwas	Timing analysis based on primitive path delay fault identification.	ICCAD	1997	DBLP DOI BibTeX RDF	primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing
1	Mariusz Rawski	Non-Disjoint Decomposition of Boolean Functions and Its Application in FPGA-oriented Technology Mapping.	EUROMICRO	1997	DBLP DOI BibTeX RDF
1	Ram K. Krishnamurthy, L. Richard Carley	Exploring the design space of mixed swing quadrail for low-power digital circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
1	Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer	AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	EXOR based synthesis, synthesis for testability, delay optimization
1	Bernhard Rohfleisch, Bernd Wurth, Kurt Antreich	Logic Clause Analysis for Delay Optimization.	DAC	1995	DBLP DOI BibTeX RDF
1	Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi	Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization.	DAC	1995	DBLP DOI BibTeX RDF
1	Kanji Hirabayashi	A parametric yield model.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	AC yield, delay defect, exponential distribution
1	Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang	A Methodology and Algorithms for Post-Placement Delay Optimization.	DAC	1994	DBLP DOI BibTeX RDF
1	Aurobindo Dasgupta, Israel Koren	An Algorithm for Area and Delay Optimization of Sequential Machines through Decomposition.	HICSS	1994	DBLP BibTeX RDF
1	Shangzhi Sun, David Hung-Chang Du, Guoliang Xue	Achieving the Shortest Clock Period by Inserting the Minimum Amount of Delay.	ISAAC	1994	DBLP DOI BibTeX RDF
1	Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler	Sequential Circuit Delay optimization Using Global Path Delays.	DAC	1993	DBLP DOI BibTeX RDF
1	Kumar Venkat	Generalized Delay Optimization of Resistive Interconnections through an Extension of Logical Effort.	ISCAS	1993	DBLP BibTeX RDF
1	Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin	Combining technology mapping and placement for delay-optimization in FPGA designs.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders